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43 条记录 (耗时 0.038 秒)

    Method and apparatus for outputting audio signal
    32.
    发明授权
    Method and apparatus for outputting audio signal 有权

    公开(公告)号：US07298204B2

    公开(公告)日：2007-11-20

    申请号：US11589616

    申请日：2006-10-30

    申请人： Jong Hoon Oh ,  Min Ki Yang ,  Il Suk Ko

    发明人： Jong Hoon Oh ,  Min Ki Yang ,  Il Suk Ko

    IPC分类号： H03F3/38

    CPC分类号： H03F3/217

    摘要： A method and an apparatus for outputting an audio signal are provided. The apparatus includes a power source; a compensator for compensating an input signal by adding the input signal to an offset value reciprocally proportional to a source voltage; a pulse width modulator for modulating an audio signal transmitted from the compensator; and an output stage for outputting the modulated audio signal. Accordingly, audio quality can be improved directly for a listener by compensating the input signal damaged by periodical voltage drops.

    Column address strobe signal generator for synchronous dynamic random access memory
    33.
    发明授权
    Column address strobe signal generator for synchronous dynamic random access memory 失效
    列地址选通信号发生器用于同步动态随机存取存储器

    公开(公告)号：US6108248A

    公开(公告)日：2000-08-22

    申请号：US828494

    申请日：1997-04-04

    申请人： Jong Hoon Oh

    发明人： Jong Hoon Oh

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/08 ,  G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/4076 ,  G11C29/02 ,  G11C7/1072 ,  G11C7/22

    摘要： A column address strobe signal generator for a synchronous dynamic random access memory with at least two internal banks, comprising a column address strobe signal active input stage for allowing a column address strobe signal to enter an active state, a column address strobe signal precharge input stage for allowing the column address strobe signal to enter a precharge state, and a bank select address input stage for selecting an external bank select address signal when a test mode signal is at an inactive state and an internal bank select address signal from a refresh counter when the test mode signal is at an active state, to allow a bank specified by the column address strobe signal to be the same as that specified by a row address strobe signal in a test mode where the refresh counter is tested, the internal bank select address signal being one of row addresses from the refresh counter. According to the present invention, the column address strobe signal generator can solve discordance between bank select addresses when the row address strobe signal and column address strobe signal are generated in the test mode operation of the SDRAM.

    摘要翻译： 一种用于具有至少两个内部组的同步动态随机存取存储器的列地址选通信号发生器，包括用于允许列地址选通信号进入有效状态的列地址选通信号有源输入级，列地址选通信号预充电输入级 用于允许列地址选通信号进入预充电状态;以及存储体选择地址输入级，用于当测试模式信号处于非活动状态时选择外部存储体选择地址信号，并且当刷新计数器处于内部存储体选择地址信号时 测试模式信号处于活动状态，允许由列地址选通信号指定的存储体与测试刷新计数器的测试模式中的行地址选通信号指定的存储体相同，内部存储体选择地址 信号是刷新计数器的行地址之一。 根据本发明，当在SDRAM的测试模式操作中产生行地址选通信号和列地址选通信号时，列地址选通信号发生器可以解决存储体选择地址之间的不一致。

    Burst page access unit usable in a synchronous DRAM and other semiconductor memory devices
    34.
    发明授权
    Burst page access unit usable in a synchronous DRAM and other semiconductor memory devices 失效
    突发页面访问单元可用于同步DRAM和其他半导体存储器件

    公开(公告)号：US5793700A

    公开(公告)日：1998-08-11

    申请号：US649764

    申请日：1996-05-15

    申请人： Jong Hoon Oh

    发明人： Jong Hoon Oh

    IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C8/00

    CPC分类号： G11C7/1018

    摘要： A burst page access unit for a semiconductor memory device which has a plurality of memory cell arrays for storing bit data therein. The burst page access unit comprises a row decoder for decoding a row address signal from an address input line in response to a row address strobe signal to select a desired on of the memory cell arrays, an internal address counter for incrementing a column address signal from the address input line by one in response to a column address strobe signal to generate an internal column address signal, and a column decoding circuit for decoding the internal column address signal from the internal address counter to select a desired one of memory cells in the memory cell array selected by the row decoder. According to the present invention, the burst page access unit can enhance the successive data access speed to increase the bandwidth of the semiconductor memory device.

    摘要翻译： 一种用于半导体存储器件的突发页访问单元，其具有用于存储位数据的多个存储单元阵列。 突发页面访问单元包括行解码器，用于响应于行地址选通信号来解码来自地址输入行的行地址信号，以选择所需的存储单元阵列;内部地址计数器，用于将列地址信号从 响应于列地址选通信号的地址输入一行一行以产生内部列地址信号;以及列解码电路，用于对来自内部地址计数器的内部列地址信号进行解码，以选择存储器中的期望的一个存储单元 单元阵列由行解码器选择。 根据本发明，突发页面访问单元可以增强连续的数据访问速度以增加半导体存储器件的带宽。

    Integrated circuit including multiple memory devices
    35.
    发明授权
    Integrated circuit including multiple memory devices 有权
    集成电路包括多个存储器件

    公开(公告)号：US08898400B2

    公开(公告)日：2014-11-25

    申请号：US11781374

    申请日：2007-07-23

    申请人： Ralf Klein ,  Jong Hoon Oh

    发明人： Ralf Klein ,  Jong Hoon Oh

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F13/42

    CPC分类号： G06F13/4239

    摘要： An integrated circuit includes a data bus and a first memory device coupled to the data bus. The first memory device is configured to provide a first signal in response to completing a power-up sequence of the first memory device. The integrated circuit includes a second memory device coupled to the data bus. The second memory device is configured to provide a second signal in response to completing a power-up sequence of the second memory device. The integrated circuit includes a controller configured to access the first memory device and the second memory device based on the first signal and the second signal.

    摘要翻译： 集成电路包括数据总线和耦合到数据总线的第一存储器件。 第一存储器件被配置为响应于完成第一存储器件的加电序列而提供第一信号。 集成电路包括耦合到数据总线的第二存储器件。 第二存储器件被配置为响应于完成第二存储器件的加电序列来提供第二信号。 集成电路包括控制器，被配置为基于第一信号和第二信号来访问第一存储器件和第二存储器件。

    DIGITAL AUDIO AMPLIFICATION DEVICE USING HARMONICS AND METHOD THEREOF
    36.
    发明申请
    DIGITAL AUDIO AMPLIFICATION DEVICE USING HARMONICS AND METHOD THEREOF 审中-公开
    数字音频放大器件使用谐波及其方法

    公开(公告)号：US20140023208A1

    公开(公告)日：2014-01-23

    申请号：US13992152

    申请日：2011-11-30

    申请人： Jong Hoon Oh ,  Kyung Whoon Cheun ,  Sung Hye Cho ,  Woo Suk Lee

    发明人： Jong Hoon Oh ,  Kyung Whoon Cheun ,  Sung Hye Cho ,  Woo Suk Lee

    IPC分类号： H03G3/20

    CPC分类号： H03G3/20 ,  H03F1/3264 ,  H03F3/217 ,  H03F2200/03

    摘要： The present invention relates to a digital audio amplification device using harmonics and a method thereof, and more specifically, the invention differentially generates characteristics of harmonics (for instance, amplitude or frequency components of harmonics) of an audio signal in order to compensate the audio signal that exceeds a preset threshold value according to the amplitude and characteristics of the audio signal, if the audio signal exceeds the preset threshold value, thereby easily improving the amplitude and the pitch of audio during digital audio amplification.

    摘要翻译： 本发明涉及使用谐波的数字音频放大装置及其方法，更具体地说，本发明差分地产生音频信号的谐波特性（例如谐波的振幅或频率分量），以便补偿音频信号 如果音频信号超过预设阈值，则根据音频信号的幅度和特性超过预设阈值，从而在数字音频放大期间容易地改善音频的幅度和音调。