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    System and method for MRAM having controlled averagable and isolatable voltage reference
    4.
    发明授权
    System and method for MRAM having controlled averagable and isolatable voltage reference 有权
    MRAM的系统和方法具有可控的可分离和可分离的电压参考

    公开(公告)号：US08675390B2

    公开(公告)日：2014-03-18

    申请号：US13278217

    申请日：2011-10-21

    申请人： Jung Pill Kim ,  Taehyun Kim

    发明人： Jung Pill Kim ,  Taehyun Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C13/004 ,  G11C5/063 ,  G11C7/08 ,  G11C11/1673 ,  G11C13/0038 ,  G11C13/0069 ,  G11C29/026 ,  G11C29/028 ,  G11C2013/0054

    摘要： A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally, different ones of the reference coupling links are removed or opened, obtaining respective different average and isolated reference voltages on the different reference lines. Optionally, different ones of the reference circuit coupling links are removed or opened, obtaining respective different averaged voltages on the reference lines, and uncoupling and isolating different reference circuits.

    摘要翻译： 存储器具有多个非易失性电阻（NVR）存储器阵列，每个存储阵列具有通过参考电路耦合到参考线的参考电压产生电路，该参考电压产生电路耦合到用于该NVR存储器阵列的读出放大器。 参考线耦合链路耦合不同NVR存储器阵列的参考线。 可选地，不同的参考耦合链路被去除或打开，在不同的参考线上获得各自不同的平均和隔离参考电压。 可选地，去除或打开不同的参考电路耦合链路，在参考线上获得各自不同的平均电压，以及解耦和隔离不同的参考电路。

    System and method for shared sensing MRAM
    7.
    发明授权
    System and method for shared sensing MRAM 有权
    共享感测MRAM的系统和方法

    公开(公告)号：US08587994B2

    公开(公告)日：2013-11-19

    申请号：US13177992

    申请日：2011-07-07

    申请人： Jung Pill Kim ,  Tae Hyun Kim

    发明人： Jung Pill Kim ,  Tae Hyun Kim

    IPC分类号： G11C11/00 ,  G11C7/02

    CPC分类号： G11C11/1693 ,  G11C11/1673

    摘要： Resistance memory cells of MRAM arrays are designated as reference cells and programmed to binary 0 and binary 1 states, reference cells from one MRAM array at binary 0 and at binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of another MRAM array, reference cells from the other MRAM array at binary 0 and binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of the one MRAM array.

    摘要翻译： 将MRAM阵列的电阻存储单元指定为参考单元，并编程为二进制0和二进制1状态，同时访问来自二进制0和二进制1的一个MRAM阵列的参考单元以获得参考电压以读取另一MRAM的电阻存储单元 数组，二进制0和二进制1的另一个MRAM阵列的参考单元被同时访问，以获得读取一个MRAM阵列的电阻存储单元的参考电压。

    LOW SENSING CURRENT NON-VOLATILE FLIP-FLOP
    8.
    发明申请
    LOW SENSING CURRENT NON-VOLATILE FLIP-FLOP 有权
    低感测电流非挥发性FLOP-FLOP

    公开(公告)号：US20130286721A1

    公开(公告)日：2013-10-31

    申请号：US13613205

    申请日：2012-09-13

    申请人： Seong-Ook Jung ,  Youngdon Jung ,  Kyungho Ryu ,  Jisu Kim ,  Jung Pill Kim ,  Seung H. Kang

    发明人： Seong-Ook Jung ,  Youngdon Jung ,  Kyungho Ryu ,  Jisu Kim ,  Jung Pill Kim ,  Seung H. Kang

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1673 ,  G11C7/065 ,  G11C11/1659 ,  G11C14/0081

    摘要： A low sensing current non volatile flip flop includes a first stage to sense a resistance difference between two magnetic tunnel junctions (MTJs) and a second stage having circuitry to amplify the output of the first stage. The output of the first stage is initially pre-charged and determined by the resistance difference of the two MTJs when the sensing operation starts. The first stage does not have a pull-up path to a source voltage (VDD), and therefore does not have a DC path from VDD to ground during the sensing operation. A slow sense enable (SE) signal slope reduces peak sensing current in the first stage. A secondary current path reduces the sensing current duration of the first stage.

    摘要翻译： 低感测电流非易失性触发器包括用于感测两个磁性隧道结（MTJ）之间的电阻差的第一级和具有用于放大第一级的输出的电路的第二级。 第一级的输出最初是预充电的，并且由感测操作开始时的两个MTJ的电阻差决定。 第一级没有到源极电压（VDD）的上拉路径，因此在感测操作期间没有从VDD到地的直流路径。 缓慢感应使能（SE）信号斜率可以降低第一级的峰值检测电流。 次级电流路径减小了第一级的感测电流持续时间。

    Reference cell write operations at a memory
    9.
    发明授权
    Reference cell write operations at a memory 有权
    在存储器中引用单元写入操作

    公开(公告)号：US08446753B2

    公开(公告)日：2013-05-21

    申请号：US12731204

    申请日：2010-03-25

    申请人： Jung Pill Kim ,  Hari M. Rao ,  Xia Li

    发明人： Jung Pill Kim ,  Hari M. Rao ,  Xia Li

    IPC分类号： G11C11/00 ,  G11C11/14 ,  G11C11/15

    CPC分类号： G11C13/004 ,  G11C8/10 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0023 ,  G11C13/0026 ,  G11C2013/0054

    摘要： A method of selecting a reference circuit for a write operation is disclosed. The method comprises selecting a reference circuit for a write operation based on an output of a row decode circuit and a column decode circuit. The reference circuit is programmed concurrently with a write operation of at least one of a plurality of memory cells in a memory array without requiring an external reference circuit write command.

    摘要翻译： 公开了一种选择用于写入操作的参考电路的方法。 该方法包括基于行解码电路和列解码电路的输出来选择用于写入操作的参考电路。 参考电路与存储器阵列中的多个存储单元中的至少一个的写入操作同时编程，而不需要外部参考电路写入命令。

    CIRCUIT AND METHOD FOR GENERATING A REFERENCE LEVEL FOR A MAGNETIC RANDOM ACCESS MEMORY ELEMENT
    10.
    发明申请
    CIRCUIT AND METHOD FOR GENERATING A REFERENCE LEVEL FOR A MAGNETIC RANDOM ACCESS MEMORY ELEMENT 有权
    用于产生磁性随机存取元件的参考电平的电路和方法

    公开(公告)号：US20130121066A1

    公开(公告)日：2013-05-16

    申请号：US13293565

    申请日：2011-11-10

    申请人： Xiaochun Zhu ,  Xia Li ,  Wenqing Wu ,  Jung Pill Kim ,  Seung H. Kang

    发明人： Xiaochun Zhu ,  Xia Li ,  Wenqing Wu ,  Jung Pill Kim ,  Seung H. Kang

    IPC分类号： G11C11/16

    CPC分类号： G11C11/16 ,  G11C5/147 ,  G11C11/1673

    摘要： A method of establishing a reference level includes providing first and second non-overlapping paths from a first node to a second node, providing first and second reference magnetic random access memory (MRAM) elements in the first path, providing third and fourth reference MRAM elements in the second path, measuring a first value indicative of a resistance between the first node and the second node, and setting the reference level based at least in part on the measured value. Also an associated reference circuit.

    摘要翻译： 建立参考水平的方法包括提供从第一节点到第二节点的第一和第二非重叠路径，在第一路径中提供第一和第二参考磁随机存取存储器（MRAM）元件，提供第三和第四参考MRAM元件 在所述第二路径中，测量表示所述第一节点和所述第二节点之间的电阻的第一值，并且至少部分地基于所述测量值来设置所述参考电平。 还有一个相关的参考电路。