Abstract:
Embodiments of the present inventions are related to systems and methods for decoding data in an LDPC decoder with flexible saturation levels for variable node probability values.
Abstract:
Systems and method relating generally to data processing, and more particularly to systems and methods for segmenting a data set and recovering the segmented data set. In one particular example, a method is disclosed that includes: querying an input data set for an actual sync mark; forcing a proxy sync mark where the actual sync mark is not found in the input data set; applying data processing to the input data set to yield a processed output; correlating a potion of the processed output with a corresponding portion of the input data set to yield a true sync location; calculating a difference between the true sync location and the location of the forced sync mark to yield an offset; re-forcing the proxy sync mark based upon the offset; and re-applying the data processing to the input data set aligned using the re-forced proxy sync mark to yield a re-processed output.
Abstract:
Systems and method relating generally to data processing, and more particularly to systems and methods for decoding information. Some disclosed systems include a first data decoding circuit, a second data decoding circuit, and a data output circuit. The second data decoding circuit is coupled to the first data decoding circuit and the data output circuit. The second data decoding circuit is operable to apply a finite alphabet iterative decoding algorithm to the first decoded output to yield a second decoded output.
Abstract:
Systems and method relating generally to data processing, and more particularly to systems and methods for fragmenting a data set and recovering the fragmented data set. As one example, a data processing system is discussed that includes: a fragmenting circuit operable to separate a data set into at least a first fragment and a second fragment; and a transfer packet formation circuit operable to: append identification information to the front of the first fragment, and at least a first M+N bits of the second fragment to the end of the first fragment to yield a first transfer fragment, and aggregate the first transfer fragment with other transfer fragments to yield an aggregate output.
Abstract:
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding.
Abstract:
Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information. Some embodiments include one or both of a multi-algorithm data encoder circuit and/or a multi-algorithm data decoder circuit. In some cases, a first algorithm encoding is applied on a first section by section basis to a user data set yield an encoded portion; and a second algorithm encoding is applied on a second section by section basis to a data set derived from a subset of the encoded portion.
Abstract:
Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability.
Abstract:
A storage system and method for interleaving a plurality of logical sectors in the storage system is disclosed. The method includes: dividing each logical sector into a predetermined number of slices; sequentially indexing the logical sectors, wherein each logical sector is identified by a logical sector index; sequentially indexing the predetermined number of slices in each logical sector, wherein each slice of the predetermined number of slices is identified by a slice index within each logical sector; and interleaving the logical sectors according to a slice interleaving process. The interleaving step further includes: a) identifying a first indexed slice of a first indexed logical sector as an initial slice; and b) identifying a subsequent slice by advancing the slice index to a subsequent index in the slice index sequence and advancing the logical sector index to a subsequent index in the logical sector index sequence.
Abstract:
Systems and method relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device. In some cases the systems include a low density parity check data decoder circuit including at least a first data decoder engine and a second data decoder engine each electrically coupled to a common circuit. The common circuit is operable to: shift a combination of both a first sub-message from the first data decoder engine and the second sub-message from the second data decoder engine to yield an shifted output, and disaggregate the shifted output to yield a third sub-message to the first data decoder engine and a fourth sub-message to the second decoder engine.