公开(公告)号：US07418534B2

公开(公告)日：2008-08-26

申请号：US10884700

申请日：2004-07-02

申请人： Mark D. Hayter ,  Joseph B. Rowlands ,  James Y. Cho

发明人： Mark D. Hayter ,  Joseph B. Rowlands ,  James Y. Cho

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G06F13/387

摘要： A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

摘要翻译： 用于网络设备的芯片上的系统。 在一个实现中，芯片上的系统可以包括（集成到单个集成电路），处理器和用于联网应用的一个或多个I / O设备。 例如，I / O设备可以包括用于耦合到网络接口的一个或多个网络接口电路。 在一个实施例中，一致性可以在芯片上的系统的边界内被强制执行，但是在边界之外不被强制执行。

公开(公告)号：US07028115B1

公开(公告)日：2006-04-11

申请号：US09680524

申请日：2000-10-06

申请人： Joseph B. Rowlands ,  Mark D. Hayter

发明人： Joseph B. Rowlands ,  Mark D. Hayter

IPC分类号： G06F13/00

CPC分类号： G06F11/141

摘要： A system may include at least a first agent and a second agent, and the first agent may be coupled to receive a block signal generated by the second agent. The block signal is indicative of whether or not the second agent is capable of participating in transactions. The first agent initiates or inhibits initiation of a transaction for which the second agent is a participant responsive to the block signal. The system may include additional agents, each configured to generate independent block signals. Other implementations may share block signals among two or more agents. For example, a memory block signal indicative of memory transactions being blocked or not blocked and an input/output (I/O) block signal indicative of I/O transactions being blocked or not blocked may be employed. In yet another implementation, a first agent may provide separate block signals to other agents.

摘要翻译： 系统可以包括至少第一代理和第二代理，并且第一代理可以被耦合以接收由第二代理产生的块信号。 块信号表示第二代理是否能够参与交易。 第一代理启动或禁止响应于块信号的第二代理是参与者的事务的启动。 系统可以包括附加的代理，每个代理被配置为产生独立的块信号。 其他实现可以在两个或更多个代理之间共享块信号。 例如，可以采用指示存储器事务被阻塞或未被阻塞的存储器块信号和指示I / O事务被阻塞或未被阻塞的输入/输出（I / O）块信号。 在又一实现中，第一代理可以向其他代理提供单独的块信号。

公开(公告)号：US07003631B2

公开(公告)日：2006-02-21

申请号：US10270480

申请日：2002-10-11

申请人： Joseph B. Rowlands

发明人： Joseph B. Rowlands

IPC分类号： G06F12/00

CPC分类号： G06F12/0817 ,  Y10S707/99952

摘要： A system comprises a plurality of nodes, each node comprising one or more coherent agents coupled to an interconnect. Ownership of a coherency block accessed by a transaction on the interconnect is transferred responsive to transmission of the address on the interconnect. The system further includes a second interconnect to which the plurality of nodes are coupled, wherein ownership of a coherency block is transferred on the second interconnect responsive to a transmission of the data comprising the coherency block on the second interconnect. A first node of the plurality of nodes issues a coherency command on the second interconnect to fetch the coherency block in response to the transaction on the interconnect within the first node, whereby ownership transfers within the first node prior to ownership transferring from another one of the plurality of nodes to the first node.

公开(公告)号：US07000076B2

公开(公告)日：2006-02-14

申请号：US10861827

申请日：2004-06-04

申请人： Joseph B. Rowlands ,  Chun H. Ning

发明人： Joseph B. Rowlands ,  Chun H. Ning

IPC分类号： G06F12/00

CPC分类号： G06F12/121 ,  G06F7/582

摘要： A random number generator circuit includes a primary circuit configured to generate a value within a first range and a secondary circuit configured to generate a value within a second range. A detector circuit detects whether or not the value from the primary circuit is within the desired output range for the random number generator circuit, and selects either the value from the primary circuit or the value from the secondary circuit in response. The second range is the desired output range and the first range encompasses the second range. In one embodiment, the primary circuit has complex harmonics but may generate values outside the desired range. The secondary circuit may have less complex harmonics, but may generate values only within the desired range. In one implementation, the random number generator circuit is used to generate a replacement way for a cache.

公开(公告)号：US06816932B2

公开(公告)日：2004-11-09

申请号：US09858778

申请日：2001-05-15

申请人： James Y. Cho ,  Joseph B. Rowlands ,  Mark H. Pearce

发明人： James Y. Cho ,  Joseph B. Rowlands ,  Mark H. Pearce

IPC分类号： G06F1338

CPC分类号： G06F13/423 ,  G06F13/4077

摘要： A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.

公开(公告)号：US06732234B1

公开(公告)日：2004-05-04

申请号：US09633544

申请日：2000-08-07

申请人： Joseph B. Rowlands ,  Michael P. Dickman

发明人： Joseph B. Rowlands ,  Michael P. Dickman

IPC分类号： G06F1200

CPC分类号： G06F12/0802 ,  G06F12/0864 ,  G06F12/0895 ,  G06F2212/2515

摘要： A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons and hit determination used for memory transactions) and either read the data from the cache storage entry (for read transactions) or write data from the transaction to the cache storage entry (for write transactions). The direct access transactions may, for example, be used to perform testing of the cache memory. As another example, direct access transactions may be used to perform a reset of the cache (by writing known data to each cache entry). In embodiments employing error checking and correction (ECC) mechanisms, direct access write transactions could also be used to recover from uncorrectable ECC errors, by overwriting the failing data to eliminate the errant data. In one embodiment, the cache may alter the state of its replacement policy in response to a direct access transaction explicitly specifying a particular way of the cache.

摘要翻译： 缓存配置为接收直接访问事务。 每个直接访问事务显式指定要响应该事务访问的高速缓存存储条目。 高速缓存可以访问高速缓存存储条目（绕过用于存储器事务的正常标签比较和命中确定），并且从缓存存储条目读取数据（用于读取事务）或将数据从事务写入缓存存储条目（对于 写交易）。 直接访问事务可以例如用于执行高速缓冲存储器的测试。 作为另一示例，可以使用直接访问事务来执行高速缓存的重置（通过将已知数据写入每个高速缓存条目）。 在采用错误检查和校正（ECC）机制的实施例中，直接访问写入事务也可以用于通过重写失败的数据来消除错误数据来从不可校正的ECC错误中恢复。 在一个实施例中，缓存可以响应于明确指定高速缓存的特定方式的直接访问事务来改变其替换策略的状态。

公开(公告)号：US06633938B1

公开(公告)日：2003-10-14

申请号：US09680525

申请日：2000-10-06

申请人： Joseph B. Rowlands ,  David L. Anderson ,  James Y. Cho

发明人： Joseph B. Rowlands ,  David L. Anderson ,  James Y. Cho

IPC分类号： G06F1200

CPC分类号： G06F13/368

摘要： A system includes two or more agents and a distributed arbitration scheme for the bus to which the agents are connected. Thus, an arbiter corresponding to each agent is provided. The arbiters are reset using a first reset signal, while the agents are reset using a separate reset signal or signals. The arbiters are concurrently released from reset when the first reset signal is deasserted, and may have a consistent reset state to provide for synchronization of the arbiters. The agents may be independently released from reset by the separate reset signals. Accordingly, the arbiters may be synchronized and may remain synchronized even if the corresponding agents are released from reset at different times, or are temporarily held in reset for any reason.

摘要翻译： 系统包括两个或多个代理和代理连接到的总线的分布式仲裁方案。 因此，提供了对应于每个代理的仲裁器。 使用第一复位信号复位仲裁器，同时使用单独的复位信号或信号复位代理。 当第一复位信号被断言时，仲裁器同时从复位释放，并且可以具有一致的复位状态以提供仲裁器的同步。 代理可以通过单独的复位信号独立地从复位释放。 因此，仲裁者可以是同步的，并且即使相应的代理在不同的时间从复位中解除，或者由于任何原因暂时保持复位，可以保持同步。

公开(公告)号：US07076582B2

公开(公告)日：2006-07-11

申请号：US10950082

申请日：2004-09-24

申请人： James Y. Cho ,  Joseph B. Rowlands ,  Mark H. Pearce

发明人： James Y. Cho ,  Joseph B. Rowlands ,  Mark H. Pearce

IPC分类号： G06F13/38 ,  H03K19/00

CPC分类号： G06F13/423 ,  G06F13/4077

摘要： A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.

公开(公告)号：US06993632B2

公开(公告)日：2006-01-31

申请号：US10857819

申请日：2004-06-01

申请人： David A. Kruckemyer ,  Joseph B. Rowlands

发明人： David A. Kruckemyer ,  Joseph B. Rowlands

IPC分类号： G06F13/00

CPC分类号： G06F12/0831

摘要： A system may include two or more agents, at least some of which may cache data. In response to a read transaction, a caching agent may snoop its cached data and provide a response in a response phase of the transaction. Particularly, the response may include an exclusive indication used to represent both exclusive and modified states within that agent. In one embodiment, the agent responding exclusive may be responsible for providing the data for a read transaction, and may transmit an indication of which of the exclusive or modified state that agent had the data in concurrent with transmitting the data.

公开(公告)号：US06865633B2

公开(公告)日：2005-03-08

申请号：US10640130

申请日：2003-08-13

申请人： Joseph B. Rowlands ,  David L. Anderson ,  James Y. Cho

发明人： Joseph B. Rowlands ,  David L. Anderson ,  James Y. Cho

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/368

CPC分类号： G06F13/368

摘要： A system includes two or more agents and a distributed arbitration scheme for the bus to which the agents are connected. Thus, an arbiter corresponding to each agent is provided. The arbiters are reset using a first reset signal, while the agents are reset using a separate reset signal or signals. The arbiters are concurrently released from reset when the first reset signal is deasserted, and may have a consistent reset state to provide for synchronization of the arbiters. The agents may be independently released from reset by the separate reset signals. Accordingly, the arbiters may be synchronized and may remain synchronized even if the corresponding agents are released from reset at different times, or are temporarily held in reset for any reason.

摘要翻译： 系统包括两个或多个代理和代理连接到的总线的分布式仲裁方案。 因此，提供了对应于每个代理的仲裁器。 使用第一复位信号复位仲裁器，同时使用单独的复位信号或信号复位代理。 当第一复位信号被断言时，仲裁器同时从复位释放，并且可以具有一致的复位状态以提供仲裁器的同步。 代理可以通过单独的复位信号独立地从复位释放。 因此，仲裁者可以是同步的，并且即使相应的代理在不同的时间被从复位中解除，也可以保持同步，或者由于任何原因暂时保持复位。