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1.发明授权Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent 失效缓存相干协议，其中独占和修改的数据从侦听代理传输到请求代理公开(公告)号：US06745297B2
公开(公告)日：2004-06-01
申请号：US09829514
申请日：2001-04-09
IPC分类号： G06F1300
CPC分类号： G06F12/0831
摘要： A system may include two or more agents, at least some of which may cache data. In response to a read transaction, a caching agent may snoop its cached data and provide a response in a response phase of the transaction. Particularly, the response may include an exclusive indication used to represent both exclusive and modified states within that agent. In one embodiment, the agent responding exclusive may be responsible for providing the data for a read transaction, and may transmit an indication of which of the exclusive or modified state that agent had the data in concurrent with transmitting the data.
摘要翻译： 系统可以包括两个或更多个代理，其中至少一些可以缓存数据。 响应于读取事务，缓存代理可以窥探其缓存的数据并在事务的响应阶段中提供响应。 特别地，响应可以包括用于表示该代理内的独占和修改状态的独占指示。 在一个实施例中，响应排他性的代理可负责提供用于读取事务的数据，并且可以发送代理具有与发送数据并发的数据的独占或修改状态中的哪一个的指示。
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公开(公告)号：US06993632B2
公开(公告)日：2006-01-31
申请号：US10857819
申请日：2004-06-01
IPC分类号： G06F13/00
CPC分类号： G06F12/0831
摘要： A system may include two or more agents, at least some of which may cache data. In response to a read transaction, a caching agent may snoop its cached data and provide a response in a response phase of the transaction. Particularly, the response may include an exclusive indication used to represent both exclusive and modified states within that agent. In one embodiment, the agent responding exclusive may be responsible for providing the data for a read transaction, and may transmit an indication of which of the exclusive or modified state that agent had the data in concurrent with transmitting the data.
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3.发明授权Link and fall-through address formation using a program counter portion selected by a specific branch address bit 失效使用由特定分支地址位选择的程序计数器部分的链接和直通地址形成公开(公告)号：US07203827B2
公开(公告)日：2007-04-10
申请号：US11069771
申请日：2005-03-01
IPC分类号： G06F9/32
CPC分类号： G06F9/324 , G06F9/30054 , G06F9/3806
摘要： A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address of a first set of bytes including a branch instruction and a second address of a second set of bytes contiguous to the first set. The least significant bits of the branch PC (those bits not included in the most significant bits of the addresses received by the circuit) are used to generate the least significant bits of the link/sequential address and to select one of the first address and the second address to supply the most significant bits.
摘要翻译： 提供链路地址/顺序地址生成电路用于生成链路/顺序地址。 该电路接收至少两个地址的最高有效位：包括分支指令的第一组字节的第一地址和与第一组相邻的第二组字节的第二地址。 分支PC的最低有效位（不包括在由电路接收的地址的最高有效位中的位）被用于生成链路/顺序地址的最低有效位，并且选择第一地址和 第二个地址提供最重要的位。
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4.发明授权Comparing operands of instructions against a replay scoreboard to detect an instruction replay and copying a replay scoreboard to an issue scoreboard 有权将指令的操作数与重放记分板进行比较，以检测指令重放并将重播记分板复制到问题记分牌公开(公告)号：US06976152B2
公开(公告)日：2005-12-13
申请号：US10066941
申请日：2002-02-04
申请人： Tse-Yu Yeh , David A. Kruckemyer , Randel P. Blake-Campos , Robert Rogenmoser , Robert Stepanian
发明人： Tse-Yu Yeh , David A. Kruckemyer , Randel P. Blake-Campos , Robert Rogenmoser , Robert Stepanian
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3859 , G06F9/3863
摘要： An apparatus for a processor includes a first scoreboard, a second scoreboard, and a control circuit coupled to the first scoreboard and the second scoreboard. The control circuit is configured to update the first scoreboard to indicate that a write is pending for a first destination register of a first instruction in response to issuing the first instruction into a first pipeline. The control circuit is configured to update the second scoreboard to indicate that the write is pending for the first destination register in response to the first instruction passing a first stage of the pipeline. Replay may be signaled for a given instruction at the first stage. In response to a replay of a second instruction, the control circuit is configured to copy a contents of the second scoreboard to the first scoreboard. In various embodiments, additional scoreboards may be used for detecting different types of dependencies.
摘要翻译： 用于处理器的装置包括第一记分板，第二记分板和耦合到第一记分板和第二记分板的控制电路。 控制电路被配置为响应于将第一指令发布到第一管道中而更新第一记分板以指示针对第一指令的第一目的地寄存器的等待写入。 控制电路被配置为响应于通过流水线的第一级的第一指令，更新第二记分板以指示该第一目的地寄存器的写暂停。 在第一阶段可能会发出给定指令的重播信号。 响应于第二指令的重放，控制电路被配置为将第二记分板的内容复制到第一记分板。 在各种实施例中，附加记分板可用于检测不同类型的依赖性。
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公开(公告)号：US09280479B1
公开(公告)日：2016-03-08
申请号：US13478100
申请日：2012-05-22
IPC分类号： G06F12/08
CPC分类号： G06F12/0871 , G06F9/3824 , G06F12/0868 , G06F12/0897 , G06F2212/1024
摘要： A memory system having increased throughput is disclosed. Specifically, the memory system includes a first level write combining queue that reduces the number of data transfers between a level one cache and a level two cache. In addition, a second level write merging buffer can further reduce the number of data transfers within the memory system. The first level write combining queue receives data from the level one cache. The second level write merging buffer receives data from the first level write combining queue. The level two cache receives data from both the first level write combining queue and the second level write merging buffer. Specifically, the first level write combining queue combines multiple store transactions from the load store units to associated addresses. In addition, the second level write merging buffer merges data from the first level write combining queue.
摘要翻译： 公开了一种具有增加的吞吐量的存储器系统。 具体来说，存储器系统包括一级写入组合队列，其减少一级缓存和二级缓存之间的数据传输次数。 此外，第二级写入合并缓冲器可以进一步减少存储器系统内的数据传输的数量。 第一级写入组合队列从一级缓存接收数据。 第二级写合并缓冲区从第一级写入组合队列接收数据。 二级缓存从第一级写入组合队列和第二级写入合并缓冲区接收数据。 具体来说，第一级写入组合队列将来自加载存储单元的多个存储事务组合到相关联的地址。 另外，第二级写入合并缓冲区合并来自第一级写入组合队列的数据。
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公开(公告)号：US08850121B1
公开(公告)日：2014-09-30
申请号：US13250544
申请日：2011-09-30
IPC分类号： G06F12/08
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/34
摘要： A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single cache access and stores the data in the load miss result buffer. The outstanding load miss buffer stores a first missed load instruction in a first primary entry. Additional missed load instructions that are dependent on the first missed load instructions are stored in dependent entries of the first primary entry or in shared entries. If a shared entry is used for a missed load instruction the shared entry is associated with the primary entry.
摘要翻译： 具有未完成的负载未命中缓冲器和加载未命中结果缓冲器的加载/存储单元被配置为从具有一级缓存的存储器系统读取数据。 丢失的加载指令存储在未完成的负载丢失缓冲器中。 加载/存储单元使用单个高速缓存访问来检索多个相关的错过加载指令的数据，并将数据存储在加载未结果缓冲器中。 未完成的负载未命中缓冲存储器将第一个缺省加载指令存储在第一个初级条目中。 依赖于第一个错过的加载指令的附加的错过加载指令被存储在第一主入口的相关条目或共享条目中。 如果共享条目用于错过加载指令，则共享条目与主条目相关联。
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7.发明授权Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines 有权使用不同的ECC编码进行回写缓存，用于清除和脏线，并重新绘制不可校正的干净线条公开(公告)号：US07437597B1
公开(公告)日：2008-10-14
申请号：US10908586
申请日：2005-05-18
IPC分类号： G06F11/10
CPC分类号： G06F11/1064
摘要： A write-back cache has error-correction code (ECC) fields storing ECC bits for cache lines. Clean cache lines are re-fetched from memory when an ECC error is detected. Dirty cache lines are corrected using the ECC bits or signal an uncorrectable error. The type of ECC code stored is different for clean and dirty lines. Clean lines use an error-detection code that can detect longer multi-bit errors than the error correction code used by dirty lines. Dirty lines use a correction code that can correct a bit error in the dirty line, while the detection code for clean lines may not be able to correct any errors. Dirty lines' ECC is optimized for correction while clean lines' ECC is optimized for detection. A single-error-correction, double-error-detection (SECDED) code may be used for dirty lines while a triple-error-detection code is used for clean lines.
摘要翻译： 回写高速缓存具有存储用于高速缓存行的ECC位的纠错码（ECC）字段。 当检测到ECC错误时，清除缓存行将从内存重新获取。 使用ECC位校正脏高速缓存行，或者发出不可纠正的错误信号。 存储的ECC代码的类型对于干净和脏线是不同的。 清洁线路使用的错误检测代码可以检测到比脏线使用的纠错码更长的多位错误。 脏线使用可以纠正脏线中的位错误的校正代码，而干线的检测代码可能无法更正任何错误。 脏线ECC被优化用于校正，而清洁线的ECC被优化用于检测。 单错误纠正，双错误检测（SECDED）代码可用于脏线，而三重检错码用于干线。
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8.发明授权Clock gating of sub-circuits within a processor execution unit responsive to instruction latency counter within processor issue circuit 失效处理器执行单元内的子电路的时钟选通响应处理器发行电路内的指令延迟计数器公开(公告)号：US06971038B2
公开(公告)日：2005-11-29
申请号：US10061695
申请日：2002-02-01
摘要： A processor may include an execution circuit, an issue circuit coupled to the execution circuit, and a clock tree for clocking circuitry in the processor. The issue circuit issues an instruction to the execution circuit, and generates a control signal responsive to whether or not the instruction is issued to the execution circuit. The execution circuit includes at least a first subcircuit and a second subcircuit. A portion of the clock tree supplies a plurality of clocks to the execution circuit, including at least a first clock clocking the first subcircuit and at least a second clock clocking the second subcircuit. The portion of the clock tree is coupled to receive the control signal for collectively conditionally gating the plurality of clock, and is also configured to individually conditionally gate at least some of the plurality of clocks responsive to activity in the respective subcircuits of the execution circuit. A system on a chip may include several processors, and one or more of the processors may be conditionally clocked at the processor level.
摘要翻译： 处理器可以包括执行电路，耦合到执行电路的发行电路，以及用于在处理器中计时电路的时钟树。 发行电路向执行电路发出指令，并且响应于是否向执行电路发出指令而生成控制信号。 执行电路至少包括第一子电路和第二子电路。 时钟树的一部分向执行电路提供多个时钟，包括至少第一时钟计时第一分支电路和至少第二时钟计时第二分支电路。 时钟树的部分被耦合以接收控制信号，用于共同有条件地选通多个时钟，并且还被配置为响应于执行电路的相应子电路中的活动而单独有条件地选择多个时钟中的至少一些。 芯片上的系统可以包括几个处理器，并且一个或多个处理器可以在处理器级别有条件地定时。
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公开(公告)号：US07296141B2
公开(公告)日：2007-11-13
申请号：US10920766
申请日：2004-08-18
申请人： David A. Kruckemyer
发明人： David A. Kruckemyer
IPC分类号： G06F9/00
CPC分类号： G06F9/3842 , G06F9/3844 , G06F9/3859
摘要： A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot of the branch instruction. The second tag may equal the first tag if the branch delay slot is unconditional for that branch, and may equal a different tag if the branch delay slot is conditional for the branch. If the branch is mispredicted, the first tag is broadcast to pipeline stages that may have speculative instructions, and the first tag is compared to tags in the pipeline stages. If the tag in a pipeline stage matches the first tag, the instruction is not cancelled. If the tag mismatches, the instruction is cancelled.
摘要翻译： 第一个标签被分配给分支指令。 根据分支指令的类型，将第二标签分配给分支指令的分支延迟时隙中的指令。 如果分支延迟时隙对于该分支是无条件的，则第二标签可以等于第一标签，并且如果分支延迟时隙对于分支是有条件的，则可以等于不同的标签。 如果分支被错误预测，则将第一标签广播到可能具有推测性指令的流水线阶段，并且将第一标签与流水线阶段中的标签进行比较。 如果流水线阶段的标签与第一个标签匹配，则该指令不会被取消。 如果标签不匹配，则说明被取消。
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10.发明授权公开(公告)号：US07219216B2
公开(公告)日：2007-05-15
申请号：US11046439
申请日：2005-01-28
申请人： David A. Kruckemyer
发明人： David A. Kruckemyer
IPC分类号： G09F9/00
CPC分类号： G06F9/3842
摘要： A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot of the branch instruction. If the branch is mispredicted, the first tag is broadcast to pipeline stages that may have speculative instructions, and the first tag is compared to tags in the pipeline stages to determine which instructions to cancel. The assignment of tags for a fetch group of concurrently fetched instructions may be performed in parallel. A plurality of branch sequence numbers may be generated, and one of the plurality may be selected for each instruction responsive to the cumulative number of branch instructions preceding that instruction within the fetch group. The selection may be further responsive to whether or not the instruction is in a conditional delay slot.
摘要翻译： 第一个标签被分配给分支指令。 根据分支指令的类型，将第二标签分配给分支指令的分支延迟时隙中的指令。 如果分支被错误预测，则将第一标签广播到可能具有推测性指令的流水线阶段，并且将第一标签与流水线阶段中的标签进行比较以确定要取消的指令。 可以并行执行并行获取的指令的取出组的标签分配。 可以生成多个分支序列号，并且响应于在取出组内的该指令之前的分支指令的累积数量，可以为每个指令选择多个分支序列号中的一个。 该选择可以进一步响应该指令是否处于条件延迟时隙。
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