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    RRAM process with roughness tuning technology
    31.
    发明授权
    RRAM process with roughness tuning technology 有权
    RRAM工艺与粗糙度调整技术

    公开(公告)号：US09583700B2

    公开(公告)日：2017-02-28

    申请号：US14746703

    申请日：2015-06-22

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Feng-Min Lee ,  Yu-Yu Lin ,  Dai-Ying Lee

    IPC: H01L45/00

    CPC classification number: H01L45/1253 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

    Abstract: The present invention relates to metal oxide based memory devices and methods for manufacturing such devices; and more particularly to memory devices having data storage materials based on metal oxide compounds fabricated with a roughness tuning process including an ion bombardment step of a bottom electrode surface prior to formation of a memory element on the bottom electrode surface. Ion bombardment improves the flatness of the bottom electrode which is beneficial in achieving a more uniform electrical field during operation, which improves device reliability.

    Abstract translation: 本发明涉及基于金属氧化物的记忆装置及其制造方法。 并且更具体地涉及具有基于金属氧化物化合物的数据存储材料的存储器件，所述金属氧化物化合物在粗糙度调整过程包括在底部电极表面上形成存储元件之前包括底部电极表面的离子轰击步骤制造。 离子轰击改善了底部电极的平坦度，这有利于在操作期间实现更均匀的电场，这提高了器件的可靠性。

    MEMORY STRUCTURE AND MANUFACTURING METHOD OF THE SAME
    32.
    发明申请
    MEMORY STRUCTURE AND MANUFACTURING METHOD OF THE SAME 有权
    其记忆结构及其制造方法

    公开(公告)号：US20160218284A1

    公开(公告)日：2016-07-28

    申请号：US14729181

    申请日：2015-06-03

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Chien-Hung Lu ,  Chin-Yi Tseng

    IPC: H01L45/00

    CPC classification number: H01L45/1253 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1633 ,  H01L45/1683

    Abstract: A memory structure including an insulating layer, a first electrode layer and a first barrier is provided. The insulating layer has a recess. The first electrode layer is formed in the recess and has a first top surface. The first barrier is formed between the insulating layer and the first electrode layer, and has a second top surface lower than the first top surface. The first top surface and the second top surface are lower than an opening of the recess.

    Abstract translation: 提供了包括绝缘层，第一电极层和第一屏障的存储结构。 绝缘层具有凹部。 第一电极层形成在凹部中并且具有第一顶表面。 第一阻挡层形成在绝缘层和第一电极层之间，并且具有比第一顶表面低的第二顶表面。 第一顶表面和第二顶表面比凹口的开口低。

    Memory structure and operation method therefor
    33.
    发明授权
    Memory structure and operation method therefor 有权
    内存结构及其操作方法

    公开(公告)号：US09196361B2

    公开(公告)日：2015-11-24

    申请号：US14085839

    申请日：2013-11-21

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Ming-Hsiu Lee ,  Feng-Min Lee ,  Yu-Yu Lin

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/79

    Abstract: Provided is an operation method applicable to a resistive memory cell including a transistor and a resistive memory element. The operation method includes: in a programming operation, generating a programming current flowing through the transistor and the resistive memory element so that a resistance state of the resistive memory element changes from a first resistance state into a second resistance state; and in an erase operation, generating an erase current from a well region of the transistor to the resistive memory element but keeping the erase current from flowing through the transistor, so that the resistance state of the resistive memory element changes from the second resistance state into the first resistance state.

    Abstract translation: 提供了一种适用于包括晶体管和电阻性存储元件的电阻式存储单元的操作方法。 操作方法包括：在编程操作中，产生流过晶体管和电阻存储元件的编程电流，使得电阻性存储元件的电阻状态从第一电阻状态变为第二电阻状态; 并且在擦除操作中，产生从晶体管的阱区到电阻存储元件的擦除电流，但是保持擦除电流不流过晶体管，使得电阻性存储元件的电阻状态从第二电阻状态变为 第一个阻力状态。

    Semiconductor structure, resistive random access memory unit structure, and manufacturing method of the semiconductor structure
    34.
    发明授权
    Semiconductor structure, resistive random access memory unit structure, and manufacturing method of the semiconductor structure 有权
    半导体结构，电阻随机存取单元结构以及半导体结构的制造方法

    公开(公告)号：US09190612B1

    公开(公告)日：2015-11-17

    申请号：US14297689

    申请日：2014-06-06

    Applicant: Macronix International Co., Ltd.

    Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Ming-Hsiu Lee

    IPC: H01L23/52 ,  H01L45/00

    CPC classification number: H01L45/1233 ,  G11C13/0007 ,  H01L45/04 ,  H01L45/08 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1633

    Abstract: A semiconductor structure, a resistive random access memory unit structure, and a manufacturing method of the semiconductor structure are provided. The semiconductor structure includes an insulating structure, a stop layer, a metal oxide layer, a resistance structure, and an electrode material layer. The insulating structure has a via, and the stop layer is formed in the via. The metal oxide layer is formed on the stop layer. The resistance structure is formed at a bottom of an outer wall of the metal oxide layer. The electrode material layer is formed on the metal oxide layer.

    Abstract translation: 提供半导体结构，电阻随机存取存储器单元结构以及半导体结构的制造方法。 半导体结构包括绝缘结构，停止层，金属氧化物层，电阻结构和电极材料层。 绝缘结构具有通孔，并且阻挡层形成在通路中。 在停止层上形成金属氧化物层。 电阻结构形成在金属氧化物层的外壁的底部。 在金属氧化物层上形成电极材料层。

    Memory device and method for operating the same
    35.
    发明授权
    Memory device and method for operating the same 有权

    公开(公告)号：US12198757B2

    公开(公告)日：2025-01-14

    申请号：US17842989

    申请日：2022-06-17

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Ming-Hsiu Lee

    IPC: G11C11/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

    Abstract: A memory device and a method for operating the same are provided. The memory device includes a plurality of resistive memory cells and a control circuitry electrically connected to the plurality of resistive memory cells. The control circuitry provides operation modes to operate the plurality of resistive memory cells. The operation modes include a first program operation and a refresh operation. The first program operation includes applying a first program bias voltage to a selected resistive memory cell of the plurality of resistive memory cells to establish a low-resistance state in the selected resistive memory cell. The first program operation establishes a first threshold voltage in the memory device. The refresh operation includes applying a refresh bias voltage to the selected resistive memory cell to refresh the selected resistive memory cell. An absolute value of the refresh bias voltage is greater than the first threshold voltage.

    Capped contact structure with variable adhesion layer thickness
    37.
    发明授权
    Capped contact structure with variable adhesion layer thickness 有权

    公开(公告)号：US11569445B2

    公开(公告)日：2023-01-31

    申请号：US17162803

    申请日：2021-01-29

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Yu Lin ,  Feng-Min Lee

    IPC: H01L45/00

    Abstract: Metal oxide based memory devices and methods for manufacturing are described herein. A method for manufacturing a memory cell includes forming a bottom adhesion layer in a via formed in an insulating layer. Forming a bottom conductive plug in the bottom adhesion layer. Forming a top adhesion layer over the bottom adhesion layer and bottom conductive plug. Forming a top conductive plug in the top adhesion layer. Wherein the thickness of the bottom and top adhesion layers may be different from one another.

    Memory device and operation method thereof
    38.
    发明授权
    Memory device and operation method thereof 有权

    公开(公告)号：US10460444B2

    公开(公告)日：2019-10-29

    申请号：US15922987

    申请日：2018-03-16

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Yu Lin ,  Feng-Min Lee

    IPC: G06T7/11 ,  G06T1/60 ,  G06K9/62 ,  G06K9/46

    Abstract: Disclosed is a memory device including plural bit lines, plural word lines and a control circuit. The bit lines are configured to receive pixel data of an image. Each word line includes plural factor units. The factor units of each word line are configured differently according to plural factors of a filter. When processing a first area of the image by the filter, the control circuit inputs the pixel data within the first area of the image to the bit lines, and enables one of the word lines for operation. When processing a second area of the image by the filter, the control circuit maintains the pixel data within the second area overlapping the first area on the bit lines, and inputs the pixel data within the second area which doesn't overlap the first area to the bit lines, and enables another one of the word lines for operation.

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