Packet Transmission Using Scheduled Prefetching

    公开(公告)号:US20220116473A1

    公开(公告)日:2022-04-14

    申请号:US17067690

    申请日:2020-10-11

    Abstract: A Network-Connected Device (NCD) includes a network interface, a host interface, an NCD memory and an NCD processor. The network interface is configured for communicating over a network. The host interface is configured for communicating with a host. The NCD memory is configured to buffer packet information that originates from the host and pertains to a packet to be transmitted to the network at a specified transmission time. The NCD processor is configured to process the buffered packet information before the specified transmission time, and to transmit the packet to the network at the specified time. Processing of the packet information and transmission of the packet are decoupled from buffering of the packet information.

    Generic Packet Header Insertion and Removal

    公开(公告)号:US20210243121A1

    公开(公告)日:2021-08-05

    申请号:US16780940

    申请日:2020-02-04

    Abstract: A communication apparatus includes a host interface, connected to a peripheral component bus so as to communicate with a CPU and a memory of a host computer. A network interface is connected to a network. Packet processing circuitry is configured to receive from a first interface a data packet including a set of one or more headers that include header fields having respective values, to identify, responsively to at least one of the header fields, a corresponding entry in a header modification table that specifies a header modification operation, to modify the set of headers in accordance with the header modification operation, to check whether the entry specifies an additional header modification operation, to output the modified set of headers if the entry does not specify an additional header modification operation, and, if the entry specifies an additional header modification operation, to feed-back the modified set of headers.

    Hardware accelerated activation of a processing unit

    公开(公告)号:US20250013489A1

    公开(公告)日:2025-01-09

    申请号:US18347643

    申请日:2023-07-06

    Abstract: In one embodiment, a network device includes a network interface to receive first packets from a network and send second packets over the network, and packet processing hardware to process a packet, accelerate activation of a given software program by performing at least one activation task of the given software program in hardware, and generate an interrupt to request a processing unit to execute the given software program to perform processing associated with the packet, and the processing unit to execute the given software program and perform processing associated with the packet, responsively to the at least one activation task performed by the packet processing hardware.

    Rule compilation schemes for fast packet classification

    公开(公告)号:US11929837B2

    公开(公告)日:2024-03-12

    申请号:US17678074

    申请日:2022-02-23

    CPC classification number: H04L1/201 G06F16/2255 G06F16/285

    Abstract: A classification apparatus includes a memory and a processor. The memory is configured to store rules corresponding to a corpus of rules in respective rule entries, each rule includes a respective set of unmasked bits having corresponding bit values, and at least some of the rules include masked bits. The rules in the corpus conform to respective Rule Patterns (RPs), each RP defining a respective sequence of masked and unmasked bits. The processor is configured to cluster the RPs, using a clustering criterion, into extended Rule Patterns (eRPs) associated with respective hash tables including buckets for storing rule entries. The clustering criterion aims to minimize an overall number of the eRPs while meeting a collision condition that depends on a specified maximal number of rule entries per bucket.

    METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR DYNAMIC LOAD BALANCING

    公开(公告)号:US20240039849A1

    公开(公告)日:2024-02-01

    申请号:US17875999

    申请日:2022-07-28

    CPC classification number: H04L47/125 H04W28/08 H04L47/32

    Abstract: Methods, systems, and computer program products for selecting packing processing cores are provided. An example system includes a plurality of packet processing cores and a load balancing unit communicatively connected to the plurality of packet processing cores. The load balancing unit is configured to receive a workflow packet including packet description data indicative of at least a packet structure and a packet priority and receive, from the plurality of packet processing cores, state data indicative of at least a utilization state and an operating state of each of the respective packet processing cores. The load balancing unit determines a selected packet processing core from amongst the plurality of packet processing cores based on the state data of the packet processing core and the packet description data of the workflow packet and transmits the workflow packet to the selected packet processing core.

    Bandwidth-control policers in a network adapter

    公开(公告)号:US11470007B2

    公开(公告)日:2022-10-11

    申请号:US17151705

    申请日:2021-01-19

    Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to communicate with a host processor running multiple application programs. The processing circuitry includes one or more bandwidth-control policers, and is configured to receive from the communication network a packet destined to given application program among the application programs running on the host processor, to associate a bandwidth-control policer with the packet, selected from among the bandwidth-control policers, and to apply the selected bandwidth-control policer to the packet to produce a policer result.

    Direct Packet Placement
    38.
    发明申请

    公开(公告)号:US20220086105A1

    公开(公告)日:2022-03-17

    申请号:US17535608

    申请日:2021-11-25

    Abstract: Communication apparatus includes a host interface and a network interface, which receives from a packet communication network at least one packet stream including a sequence of data packets, which include headers containing respective sequence numbers and data payloads containing slices of the data segment having a predefined, fixed size per slice. Packet processing circuitry is configured to receive the data packets from the network interface, and to map the data payloads of the data packets in the at least one packet stream, using a linear mapping of the sequence numbers, to respective addresses in the buffer.

    Coalescing packets based on hints generated by network adapter

    公开(公告)号:US20220021629A1

    公开(公告)日:2022-01-20

    申请号:US16932765

    申请日:2020-07-19

    Abstract: A network node includes a network adapter and a host. The network adapter is coupled to a communication network. The host includes a processor running a client process and a communication stack, and is configured to receive packets from the communication network, and classify the received packets into respective flows that are associated with respective chunks in a receive buffer, to distribute payloads of the received packets among the chunks so that payloads of packets classified to a given flow are stored in a given chunk assigned to the given flow, and to notify the communication stack of the payloads in the given chunk, for transferring the payloads in the given chunk to the client process.

Patent Agency Ranking