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公开(公告)号：US10910437B2
公开(公告)日：2021-02-02
申请号：US16420483
申请日：2019-05-23
Applicant: Micron Technology, Inc.
Inventor： Ombretta Donghi , Marcello Ravasio , Samuele Sciarrillo , Roberto Somaschini
Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.
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公开(公告)号：US10854675B2
公开(公告)日：2020-12-01
申请号：US16542136
申请日：2019-08-15
Applicant: Micron Technology, Inc.
Inventor： Samuele Sciarrillo
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.
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公开(公告)号：US20200027926A1
公开(公告)日：2020-01-23
申请号：US16542136
申请日：2019-08-15
Applicant: Micron Technology, Inc.
Inventor： Samuele Sciarrillo
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.
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公开(公告)号：US10439001B2
公开(公告)日：2019-10-08
申请号：US15858811
申请日：2017-12-29
Applicant: Micron Technology, Inc.
Inventor： Samuele Sciarrillo
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.
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公开(公告)号：US20190067372A1
公开(公告)日：2019-02-28
申请号：US16112570
申请日：2018-08-24
Applicant: Micron Technology, Inc.
Inventor： Ombretta Donghi , Marcello Ravasio , Samuele Sciarrillo , Roberto Somaschini
CPC classification number: H01L27/2463 , H01L27/2427 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.
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Patent Agency Ranking
公开(公告)号：US10163978B2
公开(公告)日：2018-12-25
申请号：US15479403
申请日：2017-04-05
Applicant: Micron Technology, Inc.
Inventor： Samuele Sciarrillo , Marcello Ravasio
Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.
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公开(公告)号：US20180138242A1
公开(公告)日：2018-05-17
申请号：US15858811
申请日：2017-12-29
Applicant: Micron Technology, Inc.
Inventor： Samuele Sciarrillo
CPC classification number: H01L27/2481 , H01L27/2427 , H01L27/2445 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1675
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.
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公开(公告)号：US20180047896A1
公开(公告)日：2018-02-15
申请号：US15792842
申请日：2017-10-25
Applicant: Micron Technology, Inc.
Inventor： Marcello Ravasio , Samuele Sciarrillo , Andrea Gotti
IPC: H01L45/00 , H01L21/3213 , H01L27/22 , H01L27/105 , H01L21/28 , H01L27/24
CPC classification number: H01L45/124 , H01L21/28 , H01L21/3213 , H01L27/1052 , H01L27/222 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/16 , H01L45/1675
Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.
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公开(公告)号：US09806129B2
公开(公告)日：2017-10-31
申请号：US14189490
申请日：2014-02-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Marcello Ravasio , Samuele Sciarrillo , Fabio Pellizzer , Innocenzo Tortorelli , Roberto Somaschini , Cristina Casellato , Riccardo Mottadelli
CPC classification number: H01L27/2463 , H01L27/2427 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/1675
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.
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公开(公告)号：US20170186816A1
公开(公告)日：2017-06-29
申请号：US15398475
申请日：2017-01-04
Applicant: Micron Technology, Inc.
Inventor： Samuele Sciarrillo
CPC classification number: H01L27/2481 , H01L27/2427 , H01L27/2445 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1675
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.
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