公开(公告)号：US11056383B2

公开(公告)日：2021-07-06

申请号：US15881539

申请日：2018-01-26

Applicant: Micron Technology, Inc.

Inventor： Roberto Somaschini ,  Alessandro Vaccaro ,  Paolo Tessariol ,  Giulio Albini

IPC: H01L27/115 ,  H01L27/105 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L27/11521

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

公开(公告)号：US20210091140A1

公开(公告)日：2021-03-25

申请号：US17069347

申请日：2020-10-13

Applicant: Micron Technology, Inc.

Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Roberto Somaschini ,  Cristina Casellato ,  Riccardo Mottadelli

IPC: H01L27/24 ,  H01L45/00

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.

公开(公告)号：US09773844B2

公开(公告)日：2017-09-26

申请号：US14970602

申请日：2015-12-16

Applicant: Micron Technology, Inc.

Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Roberto Somaschini ,  Gabriel L. Donadio

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00 ,  G11C5/06

CPC classification number: H01L27/2481 ,  G11C5/063 ,  G11C13/0002 ,  G11C2213/71 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675

Abstract: The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure.

公开(公告)号：US20150243708A1

公开(公告)日：2015-08-27

申请号：US14189490

申请日：2014-02-25

Applicant: MICRON TECHNOLOGY, INC

Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Roberto Somaschini ,  Cristina Casellato ,  Riccardo Mottadelli

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.

Abstract translation: 所公开的技术通常涉及集成电路器件，特别涉及交叉点存储器阵列及其制造方法。 在一个方面，一种制造交叉点存储器阵列的方法包括形成存储单元材料堆，所述存储单元材料堆在第一活性材料上包括第一活性材料和第二活性材料，其中第一和第二活性材料之一包括存储材料 并且第一和第二活性材料中的另一个包括选择材料。 制造交叉点阵列的方法还包括对存储单元材料堆叠进行图案化，其包括通过存储单元材料堆叠的第一和第二活性材料中的至少一个的蚀刻，在至少一个的至少一个的侧壁上形成保护衬垫 在蚀刻通过第一和第二活性材料之一之后蚀刻第一和第二活性材料，并且在第一和第二活性材料之一的侧壁上形成保护衬垫之后进一步蚀刻存储单元材料堆叠。

公开(公告)号：US20140048956A1

公开(公告)日：2014-02-20

申请号：US14066340

申请日：2013-10-29

Applicant: Micron Technology, Inc.

Inventor： Roberto Somaschini ,  Alessandro Vaccaro ,  Paolo Tessariol ,  Giulio Albini

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1052 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

公开(公告)号：US11049769B2

公开(公告)日：2021-06-29

申请号：US16111004

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Antonino Rigano ,  Roberto Somaschini

IPC: H01L21/768 ,  H01L45/00 ,  H01L27/24 ,  H01L23/522 ,  H01L21/033 ,  H01L21/311

Abstract: Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.

公开(公告)号：US10854674B2

公开(公告)日：2020-12-01

申请号：US15693102

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Roberto Somaschini ,  Cristina Casellato ,  Riccardo Mottadelli

IPC: H01L27/24 ,  H01L45/00

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.

公开(公告)号：US20190355789A1

公开(公告)日：2019-11-21

申请号：US16420483

申请日：2019-05-23

Applicant: Micron Technology, Inc.

Inventor： Ombretta Donghi ,  Marcello Ravasio ,  Samuele Sciarrillo ,  Roberto Somaschini

IPC: H01L27/24 ,  H01L45/00

Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.

公开(公告)号：US20170365642A1

公开(公告)日：2017-12-21

申请号：US15693102

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Roberto Somaschini ,  Cristina Casellato ,  Riccardo Mottadelli

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.

公开(公告)号：US20150137061A1

公开(公告)日：2015-05-21

申请号：US14086460

申请日：2013-11-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ombretta Donghi ,  Marcello Ravasio ,  Samuele Sciarrillo ,  Roberto Somaschini

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/2427 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.

Abstract translation: 公开了一种制造存储器件的方法。 一方面，该方法包括对沿第一方向延伸的第一导电线图案化。 该方法还包括在对第一导线图案化之后，在第一导电线上形成存储单元堆叠的独立柱。 形成独立的支柱包括在导电线上沉积包括选择材料和储存材料的存储单元堆叠，并且使存储单元堆叠构图以形成独立柱。 该方法还包括在图案化存储单元堆叠之后在柱上图形化第二导线，第二导线沿与第一方向交叉的第二方向延伸。