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公开(公告)号：US20220057943A1
公开(公告)日：2022-02-24
申请号：US17453787
申请日：2021-11-05
Applicant: Micron Technology, Inc.
Inventor： Brent Keeth , Naveh Malihi
Abstract: Apparatuses and methods related to tracking unauthorized access commands for memory. Identifying unauthorized memory access can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the protected region, then an access count can be incremented to signify the unauthorized access command.
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公开(公告)号：US11169717B2
公开(公告)日：2021-11-09
申请号：US16235482
申请日：2018-12-28
Applicant: Micron Technology, Inc.
Inventor： Brent Keeth , Naveh Malihi
Abstract: Apparatuses and methods related to tracking unauthorized access commands for memory. Identifying unauthorized memory access can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the protected region, then an access count can be incremented to signify the unauthorized access command.
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公开(公告)号：US20210318956A1
公开(公告)日：2021-10-14
申请号：US17356906
申请日：2021-06-24
Applicant: Micron Technology, Inc.
Inventor： Brent Keeth , Owen Fay , Chan H. Yoo , Roy E. Greeff , Matthew B. Leslie
IPC: G06F12/06 , G11C29/12 , G11C11/4093 , H01L25/18 , H01L25/065 , G06F12/02
Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.
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公开(公告)号：US20210295879A1
公开(公告)日：2021-09-23
申请号：US17340681
申请日：2021-06-07
Applicant: Micron Technology, Inc.
Inventor： Joe M Jeddeloh , Brent Keeth
Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.
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公开(公告)号：US20210257338A1
公开(公告)日：2021-08-19
申请号：US17225675
申请日：2021-04-08
Applicant: Micron Technology, Inc.
Inventor： Brent Keeth
Abstract: Systems and devices for routing signals between a memory device and an interface of a host device are described. Some memory technologies may have a defined, preconfigured interface (e.g., bumpout), where each interface terminal may have a specific location and a specific function. Using preconfigured interfaces may allow device maker and memory makers to make parts that are able to connect with one another without special designs. In some cases, a memory device may include a redistribution layer that includes a plurality of interconnects that may be configured couple channel terminals of the memory device with an interface associated with the host device.
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Patent Agency Ranking
公开(公告)号：US11094697B2
公开(公告)日：2021-08-17
申请号：US16183468
申请日：2018-11-07
Applicant: Micron Technology, Inc.
Inventor： Gloria Yang , Suraj J. Mathew , Raghunath Singanamalla , Vinay Nair , Scott J. Derner , Michael Amiel Shore , Brent Keeth , Fatma Arzum Simsek-Ege , Diem Thy N. Tran
IPC: H01L27/108 , G11C11/403 , H01L49/02 , H01L29/423 , H01L29/78 , H01L23/528 , H01L27/06 , H01L29/08 , H01L29/10
Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.
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公开(公告)号：US20210124512A1
公开(公告)日：2021-04-29
申请号：US17142837
申请日：2021-01-06
Applicant: Micron Technology, Inc.
Inventor： Brent Keeth , James Brian Johnson
IPC: G06F3/06 , H01L23/538 , H01L25/18 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C11/22 , G06F11/10 , H01L25/065 , H01L23/50 , G11C5/02 , G11C11/00
Abstract: Techniques are described herein for a reconfigurable memory device that is configurable based on the type of interposer used to couple the memory device with a host device. The reconfigurable memory device may include a plurality components for a plurality of configurations. Various components of the reconfigurable memory die may be activated/deactivated based on what type of interposer is used in the memory device. For example, if a first type of interposer is used (e.g., a high-density interposer), the data channel may be eight data pins wide. In contrast, if second type of interposer is used (e.g., an organic-based interposer), the data channel may be four data pins wide. As such, a reconfigurable memory device may include data pins and related drivers that are inactive in some configurations.
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公开(公告)号：US20200210361A1
公开(公告)日：2020-07-02
申请号：US16815586
申请日：2020-03-11
Applicant: Micron Technology, Inc.
Inventor： Brent Keeth , Richard C. Murphy , Elliott C. Cooper-Balis
IPC: G06F13/28 , G06F12/1027 , G06F3/06 , H01L23/538 , G06F13/16 , G06F12/10
Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.
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公开(公告)号：US20190341370A1
公开(公告)日：2019-11-07
申请号：US16298338
申请日：2019-03-11
Applicant: Micron Technology, Inc.
Inventor： Brent Keeth
Abstract: Systems and devices for routing signals between a memory device and an interface of a host device are described. Some memory technologies may have a defined, preconfigured interface (e.g., bumpout), where each interface terminal may have a specific location and a specific function. Using preconfigured interfaces may allow device maker and memory makers to make parts that are able to connect with one another without special designs. In some cases, a memory device may include a redistribution layer that includes a plurality of interconnects that may be configured couple channel terminals of the memory device with an interface associated with the host device.
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公开(公告)号：US10283172B2
公开(公告)日：2019-05-07
申请号：US15620490
申请日：2017-06-12
Applicant: Micron Technology, Inc.
Inventor： Joe M. Jeddeloh , Brent Keeth
IPC: G11C5/06 , G11C5/14 , G11C7/10 , H01L25/065 , G11C5/02 , G11C11/4063
Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.
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