公开(公告)号：US10910038B2

公开(公告)日：2021-02-02

申请号：US16399283

申请日：2019-04-30

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Kawamura ,  Charles L. Ingalls ,  Tae H. Kim

IPC: G11C5/14 ,  G11C11/408 ,  G11C11/4076

Abstract: An apparatus includes a plurality of main word line circuits. Each main word line circuit drives a respective global word line to one of an active state value, an intermediate voltage state, or a pre-charge state. The intermediate voltage state voltage is below the active state voltage and above the pre-charge state voltage. The memory device also includes a plurality of sub-word line drivers. Each sub-word line driver is connected to a corresponding global word line and configured to drive a respective local word line between the corresponding global word line voltage and a low voltage value. The apparatus further includes a plurality of phase drivers. Each phase driver is connected to a predetermined number of sub-word line drivers, where each of the predetermined number of sub-word line drivers connects to a different global word line.

公开(公告)号：US10854276B2

公开(公告)日：2020-12-01

申请号：US16105631

申请日：2018-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/24 ,  G11C11/4091 ,  G11C7/06 ,  G11C11/403 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/108 ,  G11C5/02 ,  G11C7/18 ,  G11C8/16 ,  G11C11/4096

Abstract: Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.

公开(公告)号：US20200295008A1

公开(公告)日：2020-09-17

申请号：US16354450

申请日：2019-03-15

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Mitsunari Sukekawa ,  Yusuke Yamamoto ,  Christopher J. Kawamura ,  Hiroaki Taketani

IPC: H01L27/108 ,  H01L23/528

Abstract: Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10535399B2

公开(公告)日：2020-01-14

申请号：US16137971

申请日：2018-09-21

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/24 ,  G11C11/4097 ,  G11C7/02 ,  G11C11/408 ,  G11C11/4094 ,  H01L27/108 ,  F21S41/25 ,  F21S41/663 ,  F21S41/265 ,  F21S41/37 ,  F21S41/125 ,  F21S41/143 ,  F21S41/255 ,  F21S41/43 ,  F21S41/64 ,  G02B27/18 ,  G11C11/4091

Abstract: Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines.

公开(公告)号：US20200005853A1

公开(公告)日：2020-01-02

申请号：US16569588

申请日：2019-09-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/22 ,  H01L27/11507 ,  G11C11/4091 ,  H01L27/11504 ,  H01L27/11509

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.

公开(公告)号：US10431283B2

公开(公告)日：2019-10-01

申请号：US16131969

申请日：2018-09-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C7/02 ,  G11C11/22 ,  G11C11/4091 ,  H01L27/11504 ,  H01L27/11509 ,  H01L27/11507 ,  G11C11/56

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.

公开(公告)号：US20190049087A1

公开(公告)日：2019-02-14

申请号：US16137971

申请日：2018-09-21

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: F21S41/25 ,  F21S41/265 ,  F21S41/663 ,  F21S41/125 ,  F21S41/143 ,  F21S41/255 ,  G02B27/18 ,  F21S41/37 ,  F21S41/43 ,  F21S41/64

CPC classification number: G11C11/4097 ,  F21S41/125 ,  F21S41/143 ,  F21S41/25 ,  F21S41/255 ,  F21S41/265 ,  F21S41/37 ,  F21S41/43 ,  F21S41/645 ,  F21S41/663 ,  G02B27/18 ,  G11C7/02 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  H01L27/108

Abstract: Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines.

公开(公告)号：US20180061481A1

公开(公告)日：2018-03-01

申请号：US15664140

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/4097 ,  G11C11/408 ,  G11C11/4094 ,  H01L27/108

CPC classification number: G11C11/4097 ,  G11C7/02 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  H01L27/108

Abstract: Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines.

公开(公告)号：US20250118358A1

公开(公告)日：2025-04-10

申请号：US18746339

申请日：2024-06-18

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Toby D. Robbs ,  Christopher J. Kawamura ,  Kang-Yong Kim

IPC: G11C11/4097 ,  G11C7/06 ,  G11C7/18

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

公开(公告)号：US12051460B2

公开(公告)日：2024-07-30

申请号：US17447490

申请日：2021-09-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tae H. Kim ,  Christopher J. Kawamura ,  Jiyun Li

IPC: G11C7/12 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/4074

CPC classification number: G11C11/4091 ,  G11C7/06 ,  G11C11/4094 ,  G11C11/4097 ,  G11C7/12 ,  G11C11/4074 ,  G11C2207/002 ,  G11C2207/005

Abstract: Apparatuses, systems, and methods for single-ended sense amplifiers. A memory device may include a number of sense amplifiers used to read the voltage of memory cells along digit lines. Double-ended sense amplifiers are coupled to two digit lines. Single-ended sense amplifiers are coupled to a single digit line. The memory cells of an edge word line of a memory array may alternately be coupled to a single-ended sense amplifier or a double-ended sense amplifier. The use of single-ended sense amplifiers may reduce a footprint for a given number of memory cells in the array.