公开(公告)号：US11264075B2

公开(公告)日：2022-03-01

申请号：US16160801

申请日：2018-10-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Debra M. Bell ,  Jeff A. McClain ,  Brian P. Callaway

IPC: G11C11/406 ,  G11C7/10

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

公开(公告)号：US11169730B2

公开(公告)日：2021-11-09

申请号：US16433891

申请日：2019-06-06

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Debra M. Bell

IPC: G11C29/00 ,  G06F3/06 ,  G06F11/10

Abstract: Methods, systems, and devices for scrub rate control for a memory device are described. For example, during a scrub operation, a memory device may perform an error correction operation on data read from a memory array of the memory device. The memory device may determine a quantity of errors detected or corrected during the scrub operation and determine a condition of the memory array based on the quantity of errors. The memory device may indicate the determined condition of the memory array to a host device. In some cases, the memory device may perform scrub operations based on one or more condition of the memory array. For example, as a condition of the memory array deteriorates, the memory device may perform scrub operations at an increased rate.

公开(公告)号：US11144214B2

公开(公告)日：2021-10-12

申请号：US16522454

申请日：2019-07-25

Applicant: Micron Technology, Inc.

Inventor： Rachael R. Carlson ,  Aparna U. Limaye ,  Diana C. Majerus ,  Debra M. Bell ,  Shea M. Morrison

IPC: G06F3/06 ,  G06F21/79 ,  G11C29/44 ,  G06F21/44 ,  H04L9/08

Abstract: Apparatuses and methods related to memory authentication. Memory devices can be authenticated utilizing authentication codes. An authentication code can be generated based on information stored in a fuse array of the memory device. The authentication code can be stored in the memory device. The stored authentication code can be compared to a captured authentication code based on fuse array information broadcast to memory components of the memory device. The authenticity of the memory device can be determined based on the comparison and can result in placing the memory device in an unlocked state.

公开(公告)号：US20210263847A1

公开(公告)日：2021-08-26

申请号：US16800356

申请日：2020-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： James S. Rehmeyer ,  Libo Wang ,  Anthony D. Veches ,  Debra M. Bell ,  Di Wu

IPC: G06F12/06 ,  G06F11/10 ,  G06F16/2455

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data may be retrieved from a memory array for the pattern matching operation by a read operation, a refresh operation, an error correction operation, and/or a pattern matching operation. The data may be retrieved from incoming data input lines instead of or in addition to the memory array. How the data is stored or retrieved for pattern matching operations may be controlled by a memory controller.

公开(公告)号：US20210173467A1

公开(公告)日：2021-06-10

申请号：US16707488

申请日：2019-12-09

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Roya Baghi ,  Erica M. Gove ,  Zahra Hosseinimakarem ,  Cheryl M. O'Donnell

IPC: G06F1/3234 ,  G11C11/56 ,  G11C16/26

Abstract: Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, a device can be coupled to a memory device with an embedded sensor. The memory device can transmit the data generated by the embedded sensor using a sensor output coupled to the device. The memory device may generate, based at least in part on a characteristic of a memory device, a signal from a sensor embedded in the memory device and transmit the signal generated by the sensor from the memory device to another device coupled to the memory device.

公开(公告)号：US20210098046A1

公开(公告)日：2021-04-01

申请号：US17076575

申请日：2020-10-21

Applicant: Micron Technology, Inc

Inventor： Kristen M. Hopper ,  Debra M. Bell ,  Aaron P. Boehm

IPC: G11C11/22 ,  G11C11/4074 ,  G06F11/34 ,  G06F11/30 ,  G11C11/4076

Abstract: Methods, systems, and devices for a current monitor for a memory device are described. A memory device may monitor potential degradation of memory cells on the device by monitoring the amount of current drawn by one or more memory cells. As the memory cells degrade, the current supplied to the memory cells may change (e.g., increase due to additional leakage current. The memory device may indirectly monitor changes in the current supplied to the memory cells by monitoring a voltage of a node of a transistor that controls the amount of current supplied to the array of memory cells. The voltage at the control node may be compared to a reference voltage to determine whether the two voltages differ by a threshold amount, indicating that the memory cells are drawing more current. The memory device may output a status indicator when the voltages differ, for example, by the threshold amount.

公开(公告)号：US20210065796A1

公开(公告)日：2021-03-04

申请号：US16553821

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Debra M. Bell ,  James S. Rehmeyer ,  Robert Bunnell ,  Nathaniel J. Meier

IPC: G11C14/00 ,  G11C17/18 ,  G11C17/16 ,  G11C11/4096 ,  G11C11/4072

Abstract: Memory devices and systems with automatic background precondition upon powerup, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a plurality of memory cells and a fuse array configured to store precondition data. The precondition data can identify a portion of the memory array, specify a predetermined precondition state, or a combination thereof. When the memory device powers on, the memory device can be configured to automatically retrieve the precondition data from the fuse array and/or to write memory cells in the portion of the memory array to the predetermined precondition state before executing an access command.

公开(公告)号：US20210026542A1

公开(公告)日：2021-01-28

申请号：US16522454

申请日：2019-07-25

Applicant: Micron Technology, Inc.

Inventor： Rachael R. Carlson ,  Aparna U. Limaye ,  Diana C. Majerus ,  Debra M. Bell ,  Shea M. Morrison

IPC: G06F3/06 ,  G11C29/44 ,  G06F21/79

Abstract: Apparatuses and methods related to memory authentication. Memory devices can be authenticated utilizing authentication codes. An authentication code can be generated based on information stored in a fuse array of the memory device. The authentication code can be stored in the memory device. The stored authentication code can be compared to a captured authentication code based on fuse array information broadcast to memory components of the memory device. The authenticity of the memory device can be determined based on the comparison and can result in placing the memory device in an unlocked state.

公开(公告)号：US10885967B2

公开(公告)日：2021-01-05

申请号：US16247277

申请日：2019-01-14

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Debra M. Bell ,  George B. Raad ,  Brian P. Callaway ,  Joshua E. Alzheimer

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/403

Abstract: A memory device may include a phase driver circuit that may output a first voltage for refreshing a plurality of memory cells. The memory device may also include a plurality of word line driver circuits that may receive the first voltage via the phase driver circuit, such that each word line driver circuit of the plurality of word line driver circuits may provide the first voltage to a respective word line associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit.

公开(公告)号：US20200342931A1

公开(公告)日：2020-10-29

申请号：US16926476

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： James R. Rehmeyer ,  George B. Raad ,  Debra M. Bell ,  Markus H. Geiger ,  Anthony D. Veches

IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/406

Abstract: Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.