公开(公告)号：US09344345B2

公开(公告)日：2016-05-17

申请号：US14219748

申请日：2014-03-19

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms ,  Wei Chen ,  Sunil S. Murthy

IPC: H01L29/82 ,  H04L12/26 ,  H01L43/12

CPC classification number: H04L43/08 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H04L43/02

Abstract: Spin torque transfer memory cells and methods of forming the same are described herein. As an example, spin torque transfer memory cells may include a self-aligning polarizer, a pinned polarizer, and a storage material formed between the self-aligning polarizer and the pinned polarizer.

Abstract translation: 旋转转矩传递存储器单元及其形成方法在此描述。 作为示例，自旋扭矩传递存储单元可以包括自对准偏振器，钉扎偏振器和形成在自对准偏振器和被钉入偏振器之间的存储材料。

公开(公告)号：US20250054560A1

公开(公告)日：2025-02-13

申请号：US18750246

申请日：2024-06-21

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms ,  Jonathan J. Strand ,  Sukneet Singh Basuta ,  Shashank Bangalore Lakshman

IPC: G11C29/50 ,  G11C11/22

Abstract: Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

公开(公告)号：US12158792B2

公开(公告)日：2024-12-03

申请号：US17740188

申请日：2022-05-09

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms

IPC: G06F1/3234 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/324 ,  G06F11/00 ,  G06F11/30 ,  G06F11/34

Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).

公开(公告)号：US12081672B2

公开(公告)日：2024-09-03

申请号：US16573855

申请日：2019-09-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jonathan D. Harms

IPC: H04L9/32 ,  G06Q20/06 ,  G06Q20/38 ,  H04L9/00

CPC classification number: H04L9/3218 ,  G06Q20/0658 ,  G06Q20/389 ,  G06Q2220/10 ,  H04L9/50 ,  H04L2209/56

Abstract: Computerized apparatus using characterized devices such as memories for intensive computational applications such as blockchain processing. In one embodiment, the computerized apparatus comprises a computational appliance (e.g., stand-alone box, server blade, plug-in card, or mobile device) that includes characterized memory devices. These memory devices are associated with a range of performances over a range of operational parameters, and can be used in conjunction with a solution density function to optimize memory searching. In one embodiment, the ledger appliance can communicate with other ledger appliances to create and/or use a blockchain ledger so as to facilitate decentralized exchanges between untrusted parties. In some variants, the ledger appliance may additionally use an application programming interface (API) to dynamically generate blockchains on the fly. Various other applications are also described (e.g., social media, machine learning, probabilistic applications and other error-tolerant applications).

公开(公告)号：US12019506B2

公开(公告)日：2024-06-25

申请号：US16581045

申请日：2019-09-24

Applicant: Micron Technology, Inc.

Inventor： Sukneet Singh Basuta ,  Shashank Bangalore Lakshman ,  Jonathan D. Harms ,  Jonathan J. Strand

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G06F12/10 ,  G11C11/22

CPC classification number: G06F11/0793 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/1068 ,  G06F12/10 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2273 ,  G11C11/2275

Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

公开(公告)号：US20240160270A1

公开(公告)日：2024-05-16

申请号：US18420211

申请日：2024-01-23

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms

IPC: G06F1/3234 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/324 ,  G06F11/00 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F1/3275 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/324 ,  G06F11/008 ,  G06F11/3037 ,  G06F11/3409 ,  G06F2201/81

Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).

公开(公告)号：US11984186B2

公开(公告)日：2024-05-14

申请号：US17454443

申请日：2021-11-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David Hulton ,  Tamara Schmitz ,  Jonathan D. Harms ,  Jeremy Chritz ,  Kevin Majerus

IPC: G11C29/00 ,  G06F3/06 ,  G06F12/02 ,  G06F12/126 ,  G06F11/10 ,  G06F12/0813 ,  G11C11/408 ,  G11C11/418 ,  G11C29/04 ,  G11C29/44 ,  H04L61/2575

CPC classification number: G11C29/76 ,  G06F3/0659 ,  G06F12/0246 ,  G06F12/126 ,  G06F11/1048 ,  G06F12/0813 ,  G11C11/408 ,  G11C11/418 ,  G11C29/04 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/787 ,  H04L61/2575

Abstract: Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map.

公开(公告)号：US11914449B2

公开(公告)日：2024-02-27

申请号：US17740130

申请日：2022-05-09

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms

IPC: G06F1/3234 ,  G06F1/08 ,  G06F1/324 ,  G06F11/34 ,  G06F11/30 ,  G06F11/00 ,  G06F1/3206

CPC classification number: G06F1/3275 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3206 ,  G06F11/008 ,  G06F11/3037 ,  G06F11/3409 ,  G06F2201/81

Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).

公开(公告)号：US11631473B2

公开(公告)日：2023-04-18

申请号：US17399872

申请日：2021-08-11

Applicant: Micron Technology, Inc.

Inventor： Shashank Bangalore Lakshman ,  Jonathan D. Harms ,  Jonathan J. Strand ,  Sukneet Singh Basuta

IPC: G11C29/00 ,  G11C29/50 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08

Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

公开(公告)号：US11585654B2

公开(公告)日：2023-02-21

申请号：US16890364

申请日：2020-06-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zahra Hosseinimakarem ,  Jonathan D. Harms ,  Alyssa N. Scarbrough ,  Dmitry Vengertsev ,  Yi Hu

IPC: G01B11/25 ,  G01B11/30

Abstract: Embodiments of the disclosure are drawn to projecting light on a surface and analyzing the scattered light to obtain spatial information of the surface and generate a three dimensional model of the surface. The three dimensional model may then be analyzed to calculate one or more surface characteristics, such as roughness. The surface characteristics may then be analyzed to provide a result, such as a diagnosis or a product recommendation. In some examples, a mobile device is used to analyze the surface.