公开(公告)号：US20220383930A1

公开(公告)日：2022-12-01

申请号：US17333203

申请日：2021-05-28

申请人： Micron Technology, Inc.

发明人： Parthasarathy Gajapathy ,  Kallol Mazumder

IPC分类号： G11C11/4076 ,  G11C11/4093 ,  G06F1/3296 ,  G06F1/3234

摘要： Systems and methods for injecting a toggling signal in a command pipeline configured to receive a multiple command types for the memory device. Toggling circuitry is configured to inject the toggling signal into at least a portion of the command pipeline when the memory device is in a power saving mode and the command pipeline is clear of valid commands. The toggling is blocked from causing writes by disabling a data strobe when a command that is invalid in the power saving mode is asserted during the power saving mode.

公开(公告)号：US10984850B2

公开(公告)日：2021-04-20

申请号：US16796696

申请日：2020-02-20

申请人： MICRON TECHNOLOGY, INC.

发明人： Kallol Mazumder

IPC分类号： G11C11/406 ,  G11C11/4076 ,  G11C11/409

摘要： An apparatus may include a semiconductor device that includes an internal clock circuit configured to receive an internal clock signal and to provide a local clock signal based on the internal clock signal. The internal clock circuit comprises a clock synchronizer configured to, in response to receipt of a command to exit a self-refresh mode, disable provision of the local clock signal by a number of cycles of the internal clock signal.

公开(公告)号：US20200081520A1

公开(公告)日：2020-03-12

申请号：US16684183

申请日：2019-11-14

申请人： MICRON TECHNOLOGY, INC.

发明人： Kallol Mazumder ,  Parthasarathy Gajapathy

IPC分类号： G06F3/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

摘要： The systems and methods provided herein relate to a command interface/memory device that supports multiple modes of command acquisition. A current command acquisition mode from a set of supported command acquisition modes that each define a corresponding command execution frequency is identified. Based upon the identified mode, clock cycles that will be used to acquire portions of a command address from are identified. The portions of the command address are acquired from the identified clock cycles and a command based upon the acquired portions of the command address is executed.

公开(公告)号：US10534686B2

公开(公告)日：2020-01-14

申请号：US14168749

申请日：2014-01-30

申请人： MICRON TECHNOLOGY, INC.

发明人： Kallol Mazumder ,  Jason M. Brown ,  Derek R. May ,  Jeffrey E. Koelling ,  Roger D. Norwood

IPC分类号： G06F11/34 ,  G11C11/408 ,  G11C11/406

摘要： Apparatuses and methods for address detection are disclosed herein. An example apparatus includes an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.

公开(公告)号：US10483970B2

公开(公告)日：2019-11-19

申请号：US16200450

申请日：2018-11-26

申请人： Micron Technology, Inc.

发明人： Kallol Mazumder ,  Myung-Ho Bae

IPC分类号： G11C7/00 ,  H03K19/00 ,  H03K3/037 ,  H03K19/20 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096

摘要： Devices and methods include receiving a command at a command interface to assert on-die termination (ODT) during an operation. An indication of a shift mode register value is received via an input. The shift mode register value corresponds to a number of shifts of a rising edge of the command in a backward direction. A delay pipeline delays the received command the number of shifts in the backward direction to generate a shifted rising edge command signal. Combination circuitry is configured to combine a falling edge command signal with the shifted rising edge command signal to form a transformed command.

公开(公告)号：US10470475B2

公开(公告)日：2019-11-12

申请号：US16197871

申请日：2018-11-21

申请人： MICRON TECHNOLOGY, INC.

发明人： Kallol Mazumder ,  Myung-Ho Bae

IPC分类号： G11C7/10 ,  A23C3/07 ,  C02F1/32 ,  A23L2/50 ,  A23L3/28 ,  C02F1/72 ,  A23C9/20 ,  G01N21/94 ,  G01N21/64 ,  G01N21/53 ,  G01N21/33 ,  C02F1/00 ,  G01N33/18 ,  C02F1/28 ,  C02F1/44

摘要： A system includes memory banks that store data and a data path coupled to the memory banks that transfers the data. The system also includes a latch that gates the data path based on a clock signal in the system. The system further includes interface circuitry coupled to the data path that sends an instruction to the memory banks to transmit the data on the data path in response to receiving a first rising edge of the clock signal. The interface circuitry also outputs gated data in response to receiving a second rising edge of the clock signal. The latch gates the data path to store the gated data in response to receiving a falling edge of the clock signal.

公开(公告)号：US20190334531A1

公开(公告)日：2019-10-31

申请号：US16392474

申请日：2019-04-23

申请人： Micron Technology, Inc.

发明人： Kallol Mazumder

IPC分类号： H03L7/081 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

摘要： Memory systems can include shifting an ODT information signal prior to passing it through a cloned DLL delay line. The shifted ODT information passes through a cloned DLL delay line to move it into a DLL domain. Meanwhile, a clock gate can use a command indication to select whether to provide a clock signal to a DLL delay line. The clock gate can block the clock signal in the absence of a read or write operation and can pass the clock signal during read or write operations. When the DLL delay line receives the clock signal, it delays the clock signal to be in the DLL domain. By locating the ODT shifter before the cloned DLL delay line, as opposed to after it, the ODT shifter doesn't need a signal passed through the DLL delay line. Preventing the clock signal from passing through the DLL delay line reduces power consumption.

公开(公告)号：US10410696B2

公开(公告)日：2019-09-10

申请号：US15857597

申请日：2017-12-28

申请人： Micron Technology, Inc.

发明人： Debra Bell ,  Kallol Mazumder

IPC分类号： G11C7/10 ,  G11C7/22 ,  G06F9/30

摘要： Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

公开(公告)号：US20190272861A1

公开(公告)日：2019-09-05

申请号：US16416425

申请日：2019-05-20

申请人： MICRON TECHNOLOGY, INC.

发明人： Debra Bell ,  Kallol Mazumder

IPC分类号： G11C7/22 ,  G06F9/30 ,  G11C7/10

摘要： Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

公开(公告)号：US20190097630A1

公开(公告)日：2019-03-28

申请号：US16200450

申请日：2018-11-26

申请人： Micron Technology, Inc.

发明人： Kallol Mazumder ,  Myung-Ho Bae

IPC分类号： H03K19/00 ,  G11C11/408 ,  G11C11/4076 ,  H03K3/037 ,  H03K19/20 ,  G11C11/4096

CPC分类号： H03K19/0005 ,  G11C5/148 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/109 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/413 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419 ,  G11C29/022 ,  G11C29/028 ,  G11C29/46 ,  G11C2207/2227 ,  G11C2207/2254 ,  H03K3/037 ,  H03K19/20

摘要： Devices and methods include receiving a command at a command interface to assert on-die termination (ODT) during an operation. An indication of a shift mode register value is received via an input. The shift mode register value corresponds to a number of shifts of a rising edge of the command in a backward direction. A delay pipeline delays the received command the number of shifts in the backward direction to generate a shifted rising edge command signal. Combination circuitry is configured to combine a falling edge command signal with the shifted rising edge command signal to form a transformed command.