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    Merged command decoder for half-frequency circuits of a memory device
    31.
    发明授权
    Merged command decoder for half-frequency circuits of a memory device 有权

    公开(公告)号：US11605408B1

    公开(公告)日：2023-03-14

    申请号：US17518153

    申请日：2021-11-03

    Applicant: Micron Technology, Inc.

    Inventor： Navya Sri Sreeram ,  Kallol Mazumder

    IPC: G11C7/22 ,  G11C7/10

    Abstract: A memory device includes a command interface configured to receive a command from a host device via multiple command address bits. The memory device also includes a merged command decoder configured to receive the command and to determine whether the command matches a bit pattern corresponding to multiple command types. The merged command decoder is also configured to, in response to the command matching the bit pattern, asserting a latch signal. The memory device also includes a latch configured to capture the multiple command address bits based at least in part on assertion of the latch signal.

    Apparatuses and methods for switching refresh state in a memory circuit
    34.
    发明授权
    Apparatuses and methods for switching refresh state in a memory circuit 有权

    公开(公告)号：US10984850B2

    公开(公告)日：2021-04-20

    申请号：US16796696

    申请日：2020-02-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kallol Mazumder

    IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/409

    Abstract: An apparatus may include a semiconductor device that includes an internal clock circuit configured to receive an internal clock signal and to provide a local clock signal based on the internal clock signal. The internal clock circuit comprises a clock synchronizer configured to, in response to receipt of a command to exit a self-refresh mode, disable provision of the local clock signal by a number of cycles of the internal clock signal.

    SYSTEMS AND METHODS FOR FREQUENCY MODE DETECTION AND IMPLEMENTATION
    35.
    发明申请
    SYSTEMS AND METHODS FOR FREQUENCY MODE DETECTION AND IMPLEMENTATION 审中-公开

    公开(公告)号：US20200081520A1

    公开(公告)日：2020-03-12

    申请号：US16684183

    申请日：2019-11-14

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kallol Mazumder ,  Parthasarathy Gajapathy

    IPC: G06F3/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

    Abstract: The systems and methods provided herein relate to a command interface/memory device that supports multiple modes of command acquisition. A current command acquisition mode from a set of supported command acquisition modes that each define a corresponding command execution frequency is identified. Based upon the identified mode, clock cycles that will be used to acquire portions of a command address from are identified. The portions of the command address are acquired from the identified clock cycles and a command based upon the acquired portions of the command address is executed.

    Apparatuses and methods for address detection
    36.
    发明授权
    Apparatuses and methods for address detection 有权

    公开(公告)号：US10534686B2

    公开(公告)日：2020-01-14

    申请号：US14168749

    申请日：2014-01-30

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kallol Mazumder ,  Jason M. Brown ,  Derek R. May ,  Jeffrey E. Koelling ,  Roger D. Norwood

    IPC: G06F11/34 ,  G11C11/408 ,  G11C11/406

    Abstract: Apparatuses and methods for address detection are disclosed herein. An example apparatus includes an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.

    Dynamic termination edge control
    37.
    发明授权
    Dynamic termination edge control 有权

    公开(公告)号：US10483970B2

    公开(公告)日：2019-11-19

    申请号：US16200450

    申请日：2018-11-26

    Applicant: Micron Technology, Inc.

    Inventor： Kallol Mazumder ,  Myung-Ho Bae

    IPC: G11C7/00 ,  H03K19/00 ,  H03K3/037 ,  H03K19/20 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096

    Abstract: Devices and methods include receiving a command at a command interface to assert on-die termination (ODT) during an operation. An indication of a shift mode register value is received via an input. The shift mode register value corresponds to a number of shifts of a rising edge of the command in a backward direction. A delay pipeline delays the received command the number of shifts in the backward direction to generate a shifted rising edge command signal. Combination circuitry is configured to combine a falling edge command signal with the shifted rising edge command signal to form a transformed command.

    PRE-DELAY ON-DIE TERMINATION SHIFTING
    39.
    发明申请
    PRE-DELAY ON-DIE TERMINATION SHIFTING 审中-公开

    公开(公告)号：US20190334531A1

    公开(公告)日：2019-10-31

    申请号：US16392474

    申请日：2019-04-23

    Applicant: Micron Technology, Inc.

    Inventor： Kallol Mazumder

    IPC: H03L7/081 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

    Abstract: Memory systems can include shifting an ODT information signal prior to passing it through a cloned DLL delay line. The shifted ODT information passes through a cloned DLL delay line to move it into a DLL domain. Meanwhile, a clock gate can use a command indication to select whether to provide a clock signal to a DLL delay line. The clock gate can block the clock signal in the absence of a read or write operation and can pass the clock signal during read or write operations. When the DLL delay line receives the clock signal, it delays the clock signal to be in the DLL domain. By locating the ODT shifter before the cloned DLL delay line, as opposed to after it, the ODT shifter doesn't need a signal passed through the DLL delay line. Preventing the clock signal from passing through the DLL delay line reduces power consumption.

    Methods and apparatuses for command shifter reduction
    40.
    发明授权
    Methods and apparatuses for command shifter reduction 有权

    公开(公告)号：US10410696B2

    公开(公告)日：2019-09-10

    申请号：US15857597

    申请日：2017-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Debra Bell ,  Kallol Mazumder

    IPC: G11C7/10 ,  G11C7/22 ,  G06F9/30

    Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

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