公开(公告)号：US11417681B2

公开(公告)日：2022-08-16

申请号：US17215308

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/768 ,  H01L27/115 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11573 ,  H01L21/3213

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

公开(公告)号：US20220181342A1

公开(公告)日：2022-06-09

申请号：US17111275

申请日：2020-12-03

Applicant: Micron Technology, Inc.

Inventor： Shruthi Kumara Vadivel ,  Yi Hu ,  Harsh Narendrakumar Jain

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The stack structure comprises a first block structure comprising stair step structures spaced from each other by crest regions, the stair step structures each comprising steps defined at horizontal edges of the tiers of the conductive structures and the insulative structures, and a second block structure horizontally neighboring the first block structure and comprising additional stair step structures spaced from one another by additional crest regions, the additional stair step structures horizontally offset from the stair step structures of the first block structure, and a slot structure extending though the stack structure and interposed between the first block structure and the second block structure. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20210358890A1

公开(公告)日：2021-11-18

申请号：US16877209

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Yi Hu

IPC: H01L25/065 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/02

Abstract: Methods for forming microelectronic devices include forming lower and upper stack structures, each comprising vertically alternating sequences of insulative and other structures arranged in tiers. Lower and upper pillar structures are formed to extend through the lower and upper stack structures, respectively. An opening is formed through the upper stack structure, and at least a portion of the other structures of the upper stack are replaced by (e.g., chemically converted into) conductive structures, which may be configured as select gate structures. Subsequently, a slit is formed, extending through both the upper and lower stack structures, and at least a portion of the other structures of the lower stack structure are replaced by a conductive material within a liner to form additional conductive structures, which may be configured as access lines (e.g., word lines). Microelectronic devices and structures and related electronic systems are also disclosed.

公开(公告)号：US20210351127A1

公开(公告)日：2021-11-11

申请号：US17385299

申请日：2021-07-26

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Harsh Narendrakumar Jain ,  Matthew J. King

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/311 ,  H01L21/762

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions has a higher top than in the second regions. The seam tops in the second regions are elevationally-coincident with or below a bottom of an uppermost of the conductive tiers. Methods are disclosed.

公开(公告)号：US20210057428A1

公开(公告)日：2021-02-25

申请号：US16550238

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Ramey M. Abdelrahaman ,  Narula Bilik ,  Daniel Billingsley ,  Zhenyu Bo ,  Joan M. Kash ,  Matthew J. King ,  Andrew Li ,  David Neumeyer ,  Wei Yeeng Ng ,  Yung K. Pak ,  Chandra Tiwari ,  Yiping Wang ,  Lance Williamson ,  Xiaosong Zhang

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.

公开(公告)号：US20210043644A1

公开(公告)日：2021-02-11

申请号：US16532019

申请日：2019-08-05

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/3213

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

公开(公告)号：US11830767B2

公开(公告)日：2023-11-28

申请号：US17402929

申请日：2021-08-16

Applicant: Micron Technology, Inc.

Inventor： Yi Hu

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/3213 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L21/76816 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/53242 ,  H10B41/27 ,  H10B43/27

Abstract: A variety of applications can include apparatus having a memory device with an array of vertical strings of memory cells for the memory device with data lines coupled to the vertical strings, where the data lines have been formed by a metal liner deposition process. In the metal liner deposition, a metal can be formed on a patterned dielectric region. The metal liner deposition process allows for construction of the height of the data lines to be well controlled with selection of a thickness for the dielectric region used in forming the metal liner. Use of a metal liner deposition provides a controlled mechanism to reduce data line capacitance by being able to select liner thickness in forming the data lines. The use of the dielectric region with the metal liner deposition can allow the fabrication of the data lines to avoid pitch double or pitch quad processes.

公开(公告)号：US11714736B2

公开(公告)日：2023-08-01

申请号：US16943890

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Brooke Spencer ,  Jennifer F. Huckaby ,  Yi Hu ,  Deepti Verma

IPC: G06F11/30 ,  H05K7/20 ,  G06F11/32

CPC classification number: G06F11/3058 ,  G06F11/3024 ,  G06F11/3037 ,  G06F11/32 ,  H05K7/20136 ,  H05K7/20209

Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with relative humidity (RH) sensors are described. Examples can include receiving from an RH sensor RH information of an environment of a processing resource or a memory resource coupled to the processing resource, or both, determining that the RH information indicates an RH level above a particular threshold for the processing resource or the memory resource, or both, and disabling one or more aspects of the processing resource or the memory resource, or both, to mitigate damage to the processing resource or the memory resource, or both, responsive to determining that the RH is above the particular threshold.

公开(公告)号：US20230207389A1

公开(公告)日：2023-06-29

申请号：US18172076

申请日：2023-02-21

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Kar Wui Thong

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/532 ,  H01L23/535 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L21/76897 ,  H01L21/31111 ,  H01L23/53257 ,  H01L23/535 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, another stack structure vertically overlying the stack structure and comprising alternating levels of other conductive structures and other insulative structures, the other stack structure comprising pillars vertically overlying the strings of memory cells, each pillar comprising an other channel material in electrical communication with the channel material of the strings of memory cells, and conductive contact structures vertically overlying the other stack structure, each conductive contact structure comprising an electrically conductive contact at least partially extending into the pillars and a portion extending outside of the pillars having a larger cross-sectional area than the pillars. Related microelectronic devices including self-aligned conductive contact structures, and related electronic systems and methods are also described.

公开(公告)号：US20210358806A1

公开(公告)日：2021-11-18

申请号：US16877233

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Kar Wui Thong

IPC: H01L21/768 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/532 ,  H01L23/535 ,  H01L21/311

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, another stack structure vertically overlying the stack structure and comprising alternating levels of other conductive structures and other insulative structures, the other stack structure comprising pillars vertically overlying the strings of memory cells, each pillar comprising an other channel material in electrical communication with the channel material of the strings of memory cells, and conductive contact structures vertically overlying the other stack structure, each conductive contact structure comprising an electrically conductive contact at least partially extending into the pillars and a portion extending outside of the pillars having a larger cross-sectional area than the pillars. Related microelectronic devices including self-aligned conductive contact structures, and related electronic systems and methods are also described.