公开(公告)号：US09276009B2

公开(公告)日：2016-03-01

申请号：US14716722

申请日：2015-05-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L29/76 ,  H01L27/115 ,  H01L23/522 ,  H01L21/768 ,  G11C16/04

CPC classification number: H01L27/1157 ,  G11C16/0483 ,  H01L21/76805 ,  H01L21/76816 ,  H01L23/5226 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Vias are formed within a stack of alternating active and insulating layers by forming a first sub stack, a second sub stack over the first sub stack, a first buffer layer therebetween and a second buffer layer under the first sub stack. An upper layer of the first sub stack is exposed through a set of vias by first and second etching processes. The first etching process forms a first set of etch vias through the second sub stack and stops at or in the first buffer layer. The second etching process etches through the first buffer layer to the upper layer of the first sub stack. A third etching process etches through the first set of etch vias, through the first sub stack and stops at or in the second buffer layer. A fourth etching process and etches through the second buffer layer.

Abstract translation: 通过在第一子堆叠之上形成第一子堆叠，第二子堆叠，其间的第一缓冲层和第一子堆叠下的第二缓冲层，形成交替的有源绝缘层和绝缘层的堆叠内的通孔。 通过第一和第二蚀刻工艺通过一组通孔暴露第一子堆叠的上层。 第一蚀刻工艺形成通过第二子堆叠的第一组蚀刻通孔，并停留在第一缓冲层中或第一缓冲层中。 第二蚀刻工艺通过第一缓冲层蚀刻到第一子堆叠的上层。 第三蚀刻工艺通过第一组蚀刻通孔蚀刻穿过第一子堆，并在第二缓冲层处或在第二缓冲层中停止。 第四蚀刻工艺并蚀刻通过第二缓冲层。

公开(公告)号：US09219074B2

公开(公告)日：2015-12-22

申请号：US14157550

申请日：2014-01-17

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D semiconductor device is provided, comprising plural memory layers vertically stacked on a substrate and parallel to each other; plural selection lines disposed on the memory layers and parallel to each other; plural bit lines disposed on the selection lines, and the bit lines arranged in parallel to each other and in perpendicular to the selection lines; plural strings formed vertically to the memory layers and the selection lines, and the strings electrically connected to the corresponding selection lines; a plurality of cells respectively defined by the strings, the selection lines and the bit lines correspondingly, and the cells arranged in a plurality of rows and columns, wherein a column direction is parallel to the bit lines while a row direction is parallel to the selection lines. The adjacent cells in the same column are electrically connected to the different bit lines.

Abstract translation: 提供了一种3D半导体器件，包括垂直堆叠在衬底上并且彼此平行的多个存储层; 多个选择线设置在存储层上并且彼此平行; 设置在选择线上的多个位线以及与选择线垂直的并行布置的位线; 垂直于存储层和选择线形成的多个串，以及电连接到相应选择线的串; 分别由串，选择线和位线相应地限定的多个单元以及布置成多个行和列的单元，其中列方向平行于位线，而行方向平行于选择 线条。 同一列中的相邻单元电连接到不同的位线。

公开(公告)号：US09202750B2

公开(公告)日：2015-12-01

申请号：US14069151

申请日：2013-10-31

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L21/76895 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory can include a plurality of memory blocks, including a first block and a second block disposed over the first block. An isolation layer is disposed in this structure, between the first and second blocks to isolate the vertical conductors in the memory kernels of the first and second blocks. Access conductors are provided outside the kernels, such as adjacent the memory blocks or through regions of the blocks that only include decoding element. The access conductors are coupled to the decoding elements in the first and second blocks, and provide for connection of the memory cells to peripheral circuits.

Abstract translation: 存储器可以包括多个存储块，包括第一块和布置在第一块上的第二块。 在该结构中，在第一和第二块之间设置隔离层，以隔离第一和第二块的存储器内核中的垂直导体。 接入导体设置在内核之外，例如邻近存储器块或通过仅包括解码元件的块的区域。 接入导体耦合到第一和第二块中的解码元件，并提供存储器单元与外围电路的连接。

公开(公告)号：US20150206882A1

公开(公告)日：2015-07-23

申请号：US14158589

申请日：2014-01-17

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L27/105 ,  G11C7/00 ,  H01L21/308 ,  H01L21/311 ,  H01L21/306 ,  H01L23/522 ,  H01L21/3213

CPC classification number: H01L21/308 ,  G11C7/00 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a plurality of stacks of alternating active strips and insulating strips. The insulating strips have effective oxide thicknesses (EOT) so that the stacks have non-simple spatial periods on a line through the alternating active strips and insulating strips. A plurality of conductive lines are arranged orthogonally over, and have surfaces conformal with, the plurality of stacks, defining a multi-layer array of interface regions at cross-points between side surfaces of the active strips in the stacks and the conductive lines. Memory elements are disposed in the interface regions, which establish a 3D array of memory cells accessible via the plurality of active strips and the plurality of conductive lines. The insulating strips in the stacks can include a first group of strips having a first EOT and a second group of strips having a second EOT that is greater than the first EOT.

Abstract translation: 存储器件包括交替的有源条和绝缘条的多个叠层。 绝缘条具有有效的氧化物厚度（EOT），使得堆叠在通过交替的有源条和绝缘条的线上具有非简单的空间周期。 在多个叠层中正交布置多个导线，并且具有与多个叠层一致的表面，在叠层和导电线中的活动带的侧表面之间的交叉点限定出界面区域的多层阵列。 存储器元件设置在接口区域中，其建立经由多个有源条带和多个导电线路可访问的存储器单元的3D阵列。 堆叠中的绝缘条可以包括具有第一EOT的第一组条带和具有大于第一EOT的第二EOT的第二组条带。

公开(公告)号：US09070447B2

公开(公告)日：2015-06-30

申请号：US14325069

申请日：2014-07-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  G11C16/04 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L27/1157 ,  G11C16/0483 ,  H01L21/76805 ,  H01L21/76816 ,  H01L23/5226 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Vias are formed within a stack of alternating active and insulating layers by forming a first sub stack, a second sub stack over the first sub stack, a first buffer layer therebetween and a second buffer layer under the first sub stack. An upper layer of the first sub stack is exposed through a set of vias by first and second etching processes. The first etching process forms a first set of etch vias through the second sub stack and stops at or in the first buffer layer. The second etching process etches through the first buffer layer to the upper layer of the first sub stack. A third etching process etches through the first set of etch vias, through the first sub stack and stops at or in the second buffer layer. A fourth etching process and etches through the second buffer layer.

Abstract translation: 通过在第一子堆叠之上形成第一子堆叠，第二子堆叠，其间的第一缓冲层和第一子堆叠下的第二缓冲层，形成交替的有源绝缘层和绝缘层的堆叠内的通孔。 通过第一和第二蚀刻工艺通过一组通孔暴露第一子堆叠的上层。 第一蚀刻工艺形成通过第二子堆叠的第一组蚀刻通孔，并停留在第一缓冲层中或第一缓冲层中。 第二蚀刻工艺通过第一缓冲层蚀刻到第一子堆叠的上层。 第三蚀刻工艺通过第一组蚀刻通孔蚀刻穿过第一子堆，并在第二缓冲层处或在第二缓冲层中停止。 第四蚀刻工艺并蚀刻通过第二缓冲层。

公开(公告)号：US09048238B1

公开(公告)日：2015-06-02

申请号：US14076376

申请日：2013-11-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5226 ,  H01L27/11548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device and a method for making it are provided. The integrated circuit device comprises plural conductive layers, plural dielectric layers and plural first stopping layers. The conductive layers are extending in a first direction. The dielectric layers are paralleled to the conductive layers, and the conductive layers and the dielectric layers are disposed in an alternative arrangement. The first stopping layers are disposed over the conductive layers and the dielectric layers. The first stopping layers make no contact with the conductive layers.

Abstract translation: 提供一种集成电路装置及其制造方法。 集成电路器件包括多个导电层，多个电介质层和多个第一阻挡层。 导电层沿第一方向延伸。 电介质层平行于导电层，并且导电层和电介质层以替代布置设置。 第一阻挡层设置在导电层和电介质层之上。 第一停止层不与导电层接触。

公开(公告)号：US09041077B2

公开(公告)日：2015-05-26

申请号：US14016308

申请日：2013-09-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen ,  Erh-Kun Lai

IPC: H01L29/76 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28008 ,  H01L21/28282 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/78

Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate and a stacked structure vertically formed on the substrate. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers, and the conductive layers and the insulating layers are interlaced. At least one of the conductive layers has a first doping segment having a first doping property and a second doping segment having a second doping property, the second doping property being different from the first doping property. The interface between the first doping segment and the second doping segment has a grain boundary.

Abstract translation: 提供了一种半导体器件及其制造方法。 半导体器件包括衬底和垂直形成在衬底上的堆叠结构。 层叠结构包括多个导电层和多个绝缘层，并且导电层和绝缘层交错。 导电层中的至少一个具有具有第一掺杂特性的第一掺杂区段和具有第二掺杂特性的第二掺杂区段，第二掺杂特性不同于第一掺杂特性。 第一掺杂段和第二掺杂段之间的界面具有晶界。

公开(公告)号：US08993429B2

公开(公告)日：2015-03-31

申请号：US14045573

申请日：2013-10-03

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L21/44 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L21/76897 ,  H01L21/768 ,  H01L21/76805 ,  H01L21/76816 ,  H01L27/11551 ,  H01L27/11575 ,  H01L27/11582

Abstract: To form an interconnect conductor structure, a stack of pads, coupled to respective active layers of a circuit, is formed. Rows of interlayer conductors are formed to extend in an X direction in contact with landing areas on corresponding pads in the stack. Adjacent rows are separated from one another in a Y direction generally perpendicular to the X direction. The interlayer conductors in a row have a first pitch in the X direction. The interlayer conductors in adjacent rows are offset in the X direction by an amount less than the first pitch. Interconnect conductors are formed over and in contact with interlayer conductors. The interconnect conductors extend in the Y direction and have a second pitch less than the first pitch.

Abstract translation: 为了形成互连导体结构，形成耦合到电路的各个有源层的一叠焊盘。 层间导体的行形成为在X方向上延伸，以与堆叠中的相应焊盘上的着陆区域接触。 相邻的行在大致垂直于X方向的Y方向上彼此分离。 一行中的层间导体在X方向上具有第一间距。 相邻行中的层间导体在X方向上偏移小于第一间距的量。 互连导体形成在层间导体上并与其接触。 互连导体在Y方向上延伸并且具有小于第一间距的第二间距。

公开(公告)号：US08558394B1

公开(公告)日：2013-10-15

申请号：US13859783

申请日：2013-04-10

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L23/50 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2924/1461 ,  H05K1/186 ,  H05K3/4644 ,  H05K3/4682 ,  H01L2924/00

Abstract: A chip stack structure and a manufacturing method thereof are provided. The chip stack structure comprises a plurality of chips, a vertical conductive line, a plurality of insulating films and a fluid. The chips are overlapped. The vertical conductive line is electrically connected to some of the chips. The vertical conductive line is disposed at the outside of a projection area of some of the chips. Each chip is disposed in one of the insulating films. The channels which are hollow are formed in one of the insulating films. The fluid is disposed in the channels.

Abstract translation: 提供了芯片堆叠结构及其制造方法。 芯片堆叠结构包括多个芯片，垂直导线，多个绝缘膜和流体。 芯片重叠。 垂直导线与某些芯片电连接。 垂直导线设置在一些芯片的投影区域的外侧。 每个芯片设置在绝缘膜之一中。 在一个绝缘膜上形成有中空的通道。 流体设置在通道中。

公开(公告)号：US11569227B2

公开(公告)日：2023-01-31

申请号：US17166081

申请日：2021-02-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen ,  Ming-Hsiu Lee

IPC: H01L27/088 ,  H01L27/11521 ,  H01L27/11556

Abstract: A three-way switch array structure including N first connectors, M second connectors, N×M third connectors and N×M three-way switches is provided, each three-way switch has a first terminal, a second terminal, a third terminal, a first switch and a second switch. Each of first terminals is disposed on one of the first connectors, each of second terminals is disposed on one of the second connectors, and each of third terminals is disposed on one of the third connectors, the first switch is disposed between the first terminal and the third terminal, and the second switch is disposed between the second terminal and the third terminal, wherein N and M are positive integers greater than or equal to 1.