利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

39 条记录 (耗时 0.021 秒)

    Semiconductor integrated circuit device tested in batches
    32.
    发明授权
    Semiconductor integrated circuit device tested in batches 有权
    半导体集成电路器件分批测试

    公开(公告)号：US06317368B1

    公开(公告)日：2001-11-13

    申请号：US09669658

    申请日：2000-09-26

    申请人： Yasuhiko Taito ,  Takeshi Hamamoto ,  Tetsuo Kato

    发明人： Yasuhiko Taito ,  Takeshi Hamamoto ,  Tetsuo Kato

    IPC分类号： G11C700

    CPC分类号： G11C16/3468

    摘要： Data are read out from sub-arrays within a memory cell array in batches. A data bus driving circuit compares the read data, and, according to the comparison result, drives the potentials of data buses with small amplitudes. A data retaining circuit retains fail information indicating the presence of a fail bit, according to the data on the data buses. The data retaining circuit responds to an externally supplied designation, and provides a pass/fail information output circuit with the fail information with large amplitude. The fail information is further output to the outside.

    摘要翻译： 批量从存储单元阵列中的子阵列中读出数据。 数据总线驱动电路将读取的数据进行比较，并且根据比较结果，驱动具有小振幅的数据总线的电位。 根据数据总线上的数据，数据保持电路保留指示故障位的存在的失败信息。 数据保持电路响应外部提供的指定，并提供具有大振幅的失败信息的通过/失败信息输出电路。 故障信息进一步输出到外部。

    Semiconductor memory device achieving fast random access
    33.
    发明授权
    Semiconductor memory device achieving fast random access 失效
    半导体存储器件实现快速随机存取

    公开(公告)号：US06781894B2

    公开(公告)日：2004-08-24

    申请号：US10392842

    申请日：2003-03-21

    申请人： Yasuhiko Taito

    发明人： Yasuhiko Taito

    IPC分类号： G11C700

    CPC分类号： G11C7/22 ,  G11C7/1048 ,  G11C11/4076 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/2281

    摘要： N-channel MOS transistors in a read gate circuit have respective sources connected to a sense amplifier activation line of a sense amplifier, not to a ground node. A read column selection line is selected prior to activation of the sense amplifier. Accordingly, paired read data lines are driven simultaneously with the activation of the sense amplifier.

    摘要翻译： 读门电路中的N沟道MOS晶体管具有连接到读出放大器的读出放大器激活线的相应源，而不连接到接地节点。 在激活读出放大器之前选择读列选择线。 因此，配对的读取数据线与感测放大器的激活同时被驱动。

    Semiconductor device provided with potential transmission line
    36.
    发明授权
    Semiconductor device provided with potential transmission line 失效
    设置有潜在传输线的半导体器件

    公开(公告)号：US06593642B2

    公开(公告)日：2003-07-15

    申请号：US09987257

    申请日：2001-11-14

    申请人： Mako Okamoto ,  Yasuhiko Taito ,  Fukashi Morishita ,  Akira Yamazaki ,  Nobuyuki Fujii

    发明人： Mako Okamoto ,  Yasuhiko Taito ,  Fukashi Morishita ,  Akira Yamazaki ,  Nobuyuki Fujii

    IPC分类号： G01F110

    CPC分类号： H01L27/10897 ,  G11C11/4074 ,  H01L27/0218

    摘要： A DRAM is provided at a portion relating to generation of a boosted potential with a filter circuit located between a detector circuit and a ring oscillator for removing a pulse-like change in level from an output signal of the detector circuit. Accordingly, temporary stop of the charge pump circuit can be prevented even when the boosted potential exceeds in a pulse-like manner the reference potential at the vicinity of the output node of the charge pump circuit, and the boosted potential can be rapidly restored to the reference potential.

    摘要翻译： 在与产生升压电位有关的部分中提供DRAM，该滤波电路位于检测器电路和环形振荡器之间，用于从检测器电路的输出信号中去除脉冲状的电平变化。 因此，即使当升压电位以类似脉冲的方式超过电荷泵电路的输出节点附近的基准电位时，也可以防止电荷泵电路的暂时停止，并且可以将升压电位迅速恢复到 参考潜力。

    Semiconductor memory device with internal power supply potential generation circuit
    37.
    发明授权
    Semiconductor memory device with internal power supply potential generation circuit 失效
    具有内部电源电位生成电路的半导体存储器件

    公开(公告)号：US06424579B1

    公开(公告)日：2002-07-23

    申请号：US09827897

    申请日：2001-04-09

    申请人： Mihoko Akiyama ,  Akira Yamazaki ,  Fukashi Morishita ,  Yasuhiko Taito ,  Nobuyuki Fujii ,  Mako Okamoto

    发明人： Mihoko Akiyama ,  Akira Yamazaki ,  Fukashi Morishita ,  Yasuhiko Taito ,  Nobuyuki Fujii ,  Mako Okamoto

    IPC分类号： G11C700

    CPC分类号： G11C5/147

    摘要： In an eDRAM, there are provided a VDC that down-converts an external power supply potential to generate an internal power supply potential for a sense amplifier band, and a VDC that down-converts the external power supply potential to generate an internal power supply potential for a column decoder. The response of the VDC is improved by increasing the through current of the VDC only during the period of time corresponding to an amplify operation of the sense amplifier. Therefore, current consumption is smaller than the conventional case where the through current of the VDC is set at a high constant level.

    摘要翻译： 在eDRAM中，提供了一个VDC，其降低转换外部电源电位以产生用于读出放大器频带的内部电源电位;以及VDC，其降低转换外部电源电位以产生内部电源电位 用于列解码器。 通过仅在对应于读出放大器的放大操作的时间段期间增加VDC的通过电流来提高VDC的响应。 因此，电流消耗小于将VDC的通电电流设定为高恒定电平的常规情况。

    Buffer circuit operating with a small through current and potential detecting circuit using the same
    38.
    发明授权
    Buffer circuit operating with a small through current and potential detecting circuit using the same 失效
    缓冲电路采用小直流电流和电位检测电路运行

    公开(公告)号：US06304120B1

    公开(公告)日：2001-10-16

    申请号：US09372592

    申请日：1999-08-12

    申请人： Yasuhiko Taito

    发明人： Yasuhiko Taito

    IPC分类号： H03K512

    CPC分类号： H03K5/125 ,  H03K5/08 ,  H03K19/0013 ,  H03K19/00315

    摘要： In a buffer circuit, a first current restricting element is connected in series with an N channel MOS transistor between an output node of a first inverter in a first stage and a line of a ground potential, and a second current restricting element is connected in series with a P channel MOS transistor between an output node of a second inverter in the first stage and a line of a power supply potential. A through current flowing in each of the first and second inverters of the first stage can be suppressed even when an input signal stays near an intermediate level.

    摘要翻译： 在缓冲电路中，第一电流限制元件与N沟道MOS晶体管串联连接在第一级的第一反相器的输出节点与地电位之间，第二电流限制元件串联连接 在第一级中的第二反相器的输出节点和电源电位线之间具有P沟道MOS晶体管。 即使当输入信号保持接近中间电平时，也可以抑制流入第一级的第一和第二反相器中的每一个的直流电流。

    Semiconductor memory device that can realize high speed data read out
    39.
    发明授权
    Semiconductor memory device that can realize high speed data read out 失效
    可实现高速数据读出的半导体存储器件

    公开(公告)号：US5852583A

    公开(公告)日：1998-12-22

    申请号：US848391

    申请日：1997-05-08

    申请人： Yasuhiko Taito ,  Shinji Kawai ,  Shinichi Kobayashi ,  Akinori Matsuo ,  Masashi Wada

    发明人： Yasuhiko Taito ,  Shinji Kawai ,  Shinichi Kobayashi ,  Akinori Matsuo ,  Masashi Wada

    IPC分类号： G11C17/00 ,  G11C8/08 ,  G11C16/06 ,  G11C8/00

    CPC分类号： G11C8/08

    摘要： Following latching of a word line select signal by a latch circuit, a transfer gate is turned off. When a word line is selected, the voltage applied to the latch circuit is shifted to a desired level to apply a desired voltage to the word line from a word line driver. As a result, a predecode signal is applied to a small size buffering circuit to be transmitted to the word line driver at a potential level between Vcc-GND. Therefore, the parasitic capacitance accompanying a predecode signal is reduced.

    摘要翻译： 在通过锁存电路锁存字线选择信号之后，转移门被关闭。 当选择字线时，施加到锁存电路的电压被移动到期望的电平，以从字线驱动器向字线施加期望的电压。 结果，将预解码信号施加到小尺寸缓冲电路，以在Vcc-GND之间的电位电平发送到字线驱动器。 因此，伴随预解码信号的寄生电容减少。