公开(公告)号：US20210351124A1

公开(公告)日：2021-11-11

申请号：US17179357

申请日：2021-02-18

Applicant: MEDIATEK INC.

Inventor： Che-Hung Kuo ,  Hsing-Chih Liu

IPC: H01L23/522 ,  H01L23/31

Abstract: An interconnect structure for a redistribution layer includes an intermediate via land pad; a cluster of upper conductive vias abutting the intermediate via land pad and electrically coupling the intermediate via land pad to an upper via land pad; and an array of lower conductive vias electrically coupling the intermediate via land pad with a lower circuit pad. The array of lower conductive vias is arranged within a horseshoe-shaped via array region extending along a perimeter of the intermediate via land pad. The array of lower conductive vias arranged within the horseshoe-shaped via array region does not overlap with the cluster of upper conductive vias.

公开(公告)号：US20200058633A1

公开(公告)日：2020-02-20

申请号：US16535019

申请日：2019-08-07

Applicant: MEDIATEK INC.

Inventor： Sheng-Mou Lin ,  Wen-Chou Wu ,  Hsing-Chih Liu

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L23/552

Abstract: The present disclosure provides a semiconductor package including a bottom package having a substrate, a radio-frequency (RF) die and a system-on-a-chip (SoC) die arranged on the substrate in a side-by-side manner, a molding compound covering the RF die and the SoC die, and an interposer over the molding compound. Connection elements and a column of signal interference shielding elements are disposed on the substrate. The connection elements surround the SoC die. The column of signal interference shielding elements is interposed between the RF die and the SoC die. A top package is mounted on the interposer.

公开(公告)号：US20180294255A1

公开(公告)日：2018-10-11

申请号：US15886813

申请日：2018-02-01

Applicant: MEDIATEK INC.

Inventor： Hsing-Chih Liu

IPC: H01L25/00 ,  H01L23/522 ,  H01L25/16 ,  H01L23/00 ,  H01L21/56

Abstract: A method for fabricating a microelectronic package is disclosed. A packaged substrate having a chip surrounded by a molding compound is prepared. An RDL structure is formed on the chip. Bump pads and SMD pads are disposed in a topmost level of metal interconnect of the RDL structure. A passivation layer covers the RDL structure. The passivation layer is subjected to a lithographic process to form bump pad openings and an SMD opening in the passivation layer. The bump pads are exposed, respectively, through the bump pad openings. The SMD pads are exposed through the SMD opening. Bumps are formed on the bump pads through the bump pad openings, respectively. A passive element is mounted on the SMD pads.

公开(公告)号：US10074628B2

公开(公告)日：2018-09-11

申请号：US15182613

申请日：2016-06-15

Applicant: MEDIATEK INC.

Inventor： Hsing-Chih Liu ,  Che-Ya Chou

IPC: H01L23/495 ,  H01L25/065 ,  H01L21/78 ,  H01L25/00 ,  H01L25/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/03 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/142 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/16225 ,  H01L2924/00015

Abstract: A system-in-package (SiP) includes a RDL structure having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first side of the RDL structure, wherein the first semiconductor die has an active surface that is in direct contact with the RDL structure; a plurality of conductive fingers on the first side of the RDL structure around the first semiconductor die; a second semiconductor die stacked directly on the first semiconductor die, wherein the second semiconductor die is electrically connected to the plurality of conductive fingers through a plurality of bond wires; and a mold cap encapsulating the first semiconductor die, the conductive fingers, the second semiconductor die, and the first side of the RDL structure.

公开(公告)号：US20160293575A1

公开(公告)日：2016-10-06

申请号：US15182613

申请日：2016-06-15

Applicant: MEDIATEK INC.

Inventor： Hsing-Chih Liu ,  Che-Ya Chou

IPC: H01L25/065 ,  H01L25/16 ,  H01L21/78 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/142 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/16225 ,  H01L2924/00015

Abstract: A system-in-package (SiP) includes a RDL structure having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first side of the RDL structure, wherein the first semiconductor die has an active surface that is in direct contact with the RDL structure; a plurality of conductive fingers on the first side of the RDL structure around the first semiconductor die; a second semiconductor die stacked directly on the first semiconductor die, wherein the second semiconductor die is electrically connected to the plurality of conductive fingers through a plurality of bond wires; and a mold cap encapsulating the first semiconductor die, the conductive fingers, the second semiconductor die, and the first side of the RDL structure.

Abstract translation: 系统级封装（SiP）包括具有第一侧和与第一侧相对的第二侧的RDL结构; 安装在所述RDL结构的第一侧上的第一半导体管芯，其中所述第一半导体管芯具有与所述RDL结构直接接触的有源表面; 在所述第一半导体管芯周围的所述RDL结构的第一侧上的多个导电指状物; 直接堆叠在第一半导体管芯上的第二半导体管芯，其中第二半导体管芯通过多个接合线电连接到多个导电指状物; 以及封装第一半导体管芯，导电指状物，第二半导体管芯和RDL结构的第一侧的模具盖。