公开(公告)号：US06207507B1

公开(公告)日：2001-03-27

申请号：US09427438

申请日：1999-10-26

申请人： Ling-Sung Wang

发明人： Ling-Sung Wang

IPC分类号： H01L21336

CPC分类号： G11C16/0475 ,  G11C11/5621 ,  G11C16/0458 ,  G11C2211/5612 ,  G11C2211/565 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/7887

摘要： A multi-level flash memory cell formed in a semiconductor substrate. The memory cell comprises: (a) a deep n-well formed in said semiconductor substrate; (b) a p-well formed within said deep n-well; (c) a first insulating layer formed over said p-well; (d) three floating gates adjacent to and insulated from one another and lying atop said first insulating layer; (e) source and drain regions formed in said p-well and on either side of said three floating gates; (f) a second insulating layer atop said three floating gates and said drain and source regions; and (g) a control gate formed atop said second insulating layer.

摘要翻译： 形成在半导体衬底中的多级闪存单元。 存储单元包括：（a）在所述半导体衬底中形成的深n阱; （b）在所述深n阱内形成的p阱; （c）形成在所述p阱上的第一绝缘层; （d）相邻并彼此绝缘并位于所述第一绝缘层顶上的三个浮动栅极; （e）在所述p阱和所述三个浮动栅极的任一侧上形成的源区和漏区; （f）在所述三个浮动栅极和所述漏极和源极区域顶部的第二绝缘层; 和（g）形成在所述第二绝缘层顶上的控制栅极。

公开(公告)号：US06190974B1

公开(公告)日：2001-02-20

申请号：US09515953

申请日：2000-02-29

申请人： Ling-Sung Wang

发明人： Ling-Sung Wang

IPC分类号： H01L218236

CPC分类号： H01L27/11253 ,  H01L21/31116

摘要： A method of fabricating a mask read-only memory. Before carrying out a code implantation, a coding mask is used as an etching mask to remove a portion of the inter-metal dielectric layer and the inter-layer dielectric layer above the coding positions, thereby forming a contact window. The code implantation is subsequently carried out so these ions can easily reach the coding positions via the contact opening.

摘要翻译： 一种制造掩模只读存储器的方法。 在进行代码注入之前，使用编码掩模作为蚀刻掩模，以去除编码位置之上的金属间介电层和层间电介质层的一部分，从而形成接触窗口。 随后执行代码注入，使得这些离子可以经由接触开口容易地到达编码位置。

公开(公告)号：US09142642B2

公开(公告)日：2015-09-22

申请号：US13371177

申请日：2012-02-10

申请人： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

发明人： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC分类号： H01L29/772 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02579 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device system, structure and method of manufacture of a source/drain with SiGe stressor material to address effects due to dopant out-diffusion are disclosed. In an embodiment, a semiconductor substrate is provided with a gate structure, and recesses for source and drain are formed on opposing sides of the gate structure. Doped stressors are embedded into the recessed source and drain regions, and a plurality of layers of undoped stressor, lightly doped stressor, highly doped stressor, and a cap layer are formed in an in-situ epitaxial process. In another embodiment the doped stressor material is boron doped epitaxial SiGe. In an alternative embodiment an additional layer of undoped stressor material is formed.

摘要翻译： 公开了一种利用SiGe应力材料制造源极/漏极的半导体器件系统，结构和方法，以解决由掺杂剂扩散引起的影响。 在一个实施例中，半导体衬底设置有栅极结构，并且用于源极和漏极的凹槽形成在栅极结构的相对侧上。 掺杂的应力源嵌入到凹陷的源极和漏极区域中，并且在原位外延工艺中形成多层未掺杂的应力源，轻掺杂应力源，高掺杂应力源和覆盖层。 在另一个实施例中，掺杂应力源材料是硼掺杂的外延SiGe。 在替代实施例中，形成附加的未掺杂应力源材料层。

公开(公告)号：US09076751B2

公开(公告)日：2015-07-07

申请号：US13221594

申请日：2011-08-30

申请人： Jia Yang Ko ,  Ying-Han Chiou ,  Ling-Sung Wang

发明人： Jia Yang Ko ,  Ying-Han Chiou ,  Ling-Sung Wang

IPC分类号： G01R31/10 ,  H01L23/34 ,  G01R31/28 ,  H01L21/66

CPC分类号： H01L23/345 ,  G01R31/2875 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices with self-heating structures, methods of manufacture thereof, and testing methods are disclosed. In one embodiment, a semiconductor device includes a workpiece, an active electrical structure disposed over the workpiece, and at least one self-heating structure disposed proximate the active electrical structure. The active electrical structure may include a capacitor, a resistor, a conductive line, a segment of a conductive line, a transistor, or a combination thereof.

摘要翻译： 公开了具有自热结构的半导体器件，其制造方法和测试方法。 在一个实施例中，半导体器件包括工件，设置在工件上方的有源电气结构以及靠近有源电气结构设置的至少一个自热结构。 有源电结构可以包括电容器，电阻器，导电线，导电线段，晶体管或其组合。

公开(公告)号：US08766256B2

公开(公告)日：2014-07-01

申请号：US13494157

申请日：2012-06-12

申请人： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

发明人： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/76895 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/1104 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/7848

摘要： The present disclosure relates to a device and method for fabricating a semiconductor memory device arrangement comprising a butted a contact arrangement configured to couple two transistors, wherein an active area of a first transistor is coupled to an active gate of a second transistor. The active gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active area of the first transistor and an isolation layer formed about the first transistor. The butted a contact arrangement results in a decreased contact resistance for the butted contact as compared to previous methods.

摘要翻译： 本公开涉及一种用于制造半导体存储器件装置的器件和方法，该器件包括配置成耦合两个晶体管的对接触点布置，其中第一晶体管的有源区域耦合到第二晶体管的有源栅极。 第二晶体管的有源栅极由包括第一晶体管的伪栅极的栅极材料形成，并且被配置为跨越第一晶体管的有源区域和围绕第一晶体管形成的隔离层之间的边界。 与之前的方法相比，对接的接触布置导致对接触点的接触电阻降低。

公开(公告)号：US20140054716A1

公开(公告)日：2014-02-27

申请号：US13594620

申请日：2012-08-24

申请人： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

发明人： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC分类号： H01L27/092 ,  H01L27/088

CPC分类号： H01L27/1104 ,  H01L27/0207

摘要： A device includes a first pull-up transistor, a second pull-up transistor, and a dummy gate electrode between the first and the second pull-up transistors. The first and the second pull-up transistors are included in a first Static Random Access Memory (SRAM) cell.

摘要翻译： 器件包括在第一和第二上拉晶体管之间的第一上拉晶体管，第二上拉晶体管和虚拟栅电极。 第一和第二上拉晶体管被包括在第一静态随机存取存储器（SRAM）单元中。

公开(公告)号：US20130087885A1

公开(公告)日：2013-04-11

申请号：US13269401

申请日：2011-10-07

申请人： Jiun-Jie Huang ,  Ling-Sung Wang ,  Chi-Yen Lin

发明人： Jiun-Jie Huang ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC分类号： H01L29/92

CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A via-hole region is employed to enclose the metal-oxide-metal capacitor so as to remove the moisture stored in the low k dielectric material.

摘要翻译： 金属氧化物 - 金属电容器包括第一电极，第二电极，多个第一指状物和多个第二指状物。 每个第一指状物及其相应的第二指状物平行并由低k电介质材料隔开。 采用通孔区域来包围金属氧化物 - 金属电容器，以去除存储在低k电介质材料中的水分。

公开(公告)号：US20130002263A1

公开(公告)日：2013-01-03

申请号：US13175263

申请日：2011-07-01

申请人： Huang Jiun-Jie ,  Chi-Yen Lin ,  Ling-Sung Wang ,  Chih-Fu Chang

发明人： Huang Jiun-Jie ,  Chi-Yen Lin ,  Ling-Sung Wang ,  Chih-Fu Chang

IPC分类号： G01R31/12

CPC分类号： G01R31/2856

摘要： A method of reliability testing of a semiconductor device is described. The embodiment, includes providing a capacitor including an insulating layer interposing two conductive layers. A plurality of voltages are provided to the capacitor including providing a first voltage and a second voltage greater than the first voltage. A leakage associated with the capacitor is measured while applying the second voltage. In an embodiment, the leakage measured while applying the second voltage indicates that a failure of the insulating layer of the capacitor has occurred. In an embodiment, the capacitor is an inter-digitated metal-oxide-metal (MOM) capacitor. The reliability testing may be correlated to TDDB test results. The reliability testing may be performed at a wafer-level.

摘要翻译： 描述了半导体器件的可靠性测试方法。 该实施例包括提供包括插入两个导电层的绝缘层的电容器。 向电容器提供多个电压，包括提供大于第一电压的第一电压和第二电压。 在施加第二电压的同时测量与电容器相关的泄漏。 在一个实施例中，在施加第二电压时测量的泄漏表明电容器的绝缘层发生故障。 在一个实施例中，电容器是数字化的金属氧化物金属（MOM）电容器。 可靠性测试可能与TDDB测试结果相关。 可以在晶片级进行可靠性测试。

公开(公告)号：US08207532B2

公开(公告)日：2012-06-26

申请号：US10661793

申请日：2003-09-12

申请人： Chi-An Kao ,  Yung-Chang Chang ,  Yu-Ping Chang ,  Ling-Sung Wang

发明人： Chi-An Kao ,  Yung-Chang Chang ,  Yu-Ping Chang ,  Ling-Sung Wang

IPC分类号： H01L23/58

CPC分类号： H01L22/20 ,  H01L21/31116 ,  H01L21/76802

摘要： A new method is provided for the creation of a hole through a layer of insulating material. The method provides for combining a feed-forward method with a feed backward method and a high-polymer based hole profile, in order to establish a hole of a constant Critical Dimension for the hole bottom, making the CD of the hole bottom independent of the CD of the opening created through the overlying developed layer of photoresist and independent of the thickness of the layer of insulator material after CMP has been applied to the surface of the insulation layer.

摘要翻译： 提供了一种通过绝缘材料层产生孔的新方法。 该方法提供了前馈方法与进料反向法和高聚合物基孔分布的组合，以便为孔底建立恒定临界尺寸的孔，使得孔底的CD独立于 通过上覆显影层的光致抗蚀剂形成的开口的CD和CMP之后的绝缘体材料层的厚度独立于绝缘层的表面。

公开(公告)号：US06500728B1

公开(公告)日：2002-12-31

申请号：US10154741

申请日：2002-05-24

申请人： Ling-Sung Wang

发明人： Ling-Sung Wang

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： A method of fabricating a dual-oxide STI comprising the following steps. A structure having an STI opening formed therein is provided. An HDP silicon oxide layer portion is formed within the STI opening, partially filling the STI opening. A planarized HDP silicon-rich-oxide cap layer is formed upon the HDP silicon oxide layer portion, filling the STI opening to form the dual-oxide STI, whereby any unlanded contact window formed through an overlying interlevel dielectric layer exposing a portion of the dual-oxide STI only exposes a portion of the HDP silicon-rich-oxide cap layer.

摘要翻译： 一种制造双氧化物STI的方法，包括以下步骤。 提供其中形成有STI开口的结构。 在STI开口内形成HDP氧化硅层部分，部分填充STI开口。 在HDP氧化硅层部分上形成平坦化的HDP富氧氧化物覆盖层，填充STI开口以形成双氧化物STI，由此通过覆盖的层间电介质层形成的任何未上接触窗口暴露了双重氧化物层 氧化物STI仅暴露一部分HDP富氧氧化物覆盖层。