公开(公告)号：US20100133694A1

公开(公告)日：2010-06-03

申请号：US12701045

申请日：2010-02-05

申请人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

发明人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

IPC分类号： H01L23/48 ,  H01L23/498

CPC分类号： H01L23/5329 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.

摘要翻译： 公开了包括金属互连的金属互连和IC芯片。 该方法的一个实施例可以包括提供直到并包括中间线（MOL）层的集成电路（IC）芯片，MOL层包括定位在第一电介质内的触点; 使第一电介质凹陷，使得接触延伸超过第一电介质的上表面; 在所述第一电介质上形成第二电介质，使得所述第二电介质围绕所述接触的至少一部分，所述第二电介质具有比所述第一电介质低的介电常数; 在所述第二电介质上形成平坦化层; 通过平坦化层形成开口并进入到接触件的第二电介质中; 并在开口中形成金属以形成金属互连。

公开(公告)号：US07718525B2

公开(公告)日：2010-05-18

申请号：US11770928

申请日：2007-06-29

申请人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

发明人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

IPC分类号： H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.

摘要翻译： 公开了形成金属互连的方法和包括金属互连的IC芯片。 该方法的一个实施例可以包括提供直到并包括中间线（MOL）层的集成电路（IC）芯片，MOL层包括定位在第一电介质内的触点; 使第一电介质凹陷，使得接触延伸超过第一电介质的上表面; 在所述第一电介质上形成第二电介质，使得所述第二电介质围绕所述接触的至少一部分，所述第二电介质具有比所述第一电介质更低的介电常数; 在所述第二电介质上形成平坦化层; 通过平坦化层形成开口并进入到接触件的第二电介质中; 并在开口中形成金属以形成金属互连。

公开(公告)号：US07645694B2

公开(公告)日：2010-01-12

申请号：US12143445

申请日：2008-06-20

申请人： Matthew E. Colburn ,  Dmitriy Shneyder ,  Shahab Siddiqui

发明人： Matthew E. Colburn ,  Dmitriy Shneyder ,  Shahab Siddiqui

IPC分类号： H01L21/00

CPC分类号： G03F7/168 ,  G03F7/325 ,  Y10S438/922 ,  Y10S977/733 ,  Y10S977/734

摘要： Methods of developing or removing a select region of block copolymer films using a polar supercritical solvent to dissolve a select portion are disclosed. In one embodiment, the polar supercritical solvent includes chlorodifluoromethane, which may be exposed to the block copolymer film using supercritical carbon dioxide (CO2) as a carrier or chlorodiflouromethane itself in supercritical form. The invention also includes a method of forming a nano-structure including exposing a polymeric film to a polar supercritical solvent to develop at least a portion of the polymeric film. The invention also includes a method of removing a poly(methyl methacrylate-b-styrene) (PMMA-b-S) based resist using a polar supercritical solvent.

摘要翻译： 公开了使用极性超临界溶剂显影或除去嵌段共聚物膜的选择区域以溶解选择部分的方法。 在一个实施方案中，极性超临界溶剂包括氯二氟甲烷，其可以使用超临界二氧化碳（CO 2）作为载体或氯二氟乙烷本身以超临界形式暴露于嵌段共聚物膜。 本发明还包括形成纳米结构的方法，包括将聚合物膜暴露于极性超临界溶剂以形成至少一部分聚合物膜。 本发明还包括使用极性超临界溶剂除去聚（甲基丙烯酸甲酯-b-苯乙烯）（PMMA-b-S）基抗蚀剂的方法。

公开(公告)号：US07531444B2

公开(公告)日：2009-05-12

申请号：US10906267

申请日：2005-02-11

申请人： Christos D. Dimitrakopoulos ,  Daniel C. Edelstein ,  Vincent J. McGahay ,  Satyanarayana V. Nittta ,  Kevin S. Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

发明人： Christos D. Dimitrakopoulos ,  Daniel C. Edelstein ,  Vincent J. McGahay ,  Satyanarayana V. Nittta ,  Kevin S. Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

IPC分类号： H01L21/4763

CPC分类号： H01L21/76832 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76834

摘要： A method of forming airgaps is provided where a blocking mask is applied to a substrate to shield a portion of the substrate from a beam of energy. After irradiation, the blocking mask is removed and a capping material is applied to the substrate. Alternatively, the capping material may be applied before irradiation. The capping material is perforated to allow an etchant to pass therethrough to the substrate below the capping material. The exposed portions of the substrate are removed from underneath the capping material by etching. The capping material is then sealed leaving sealed airgaps within the substrate.

摘要翻译： 提供了一种形成气隙的方法，其中将阻挡掩模施加到基板以将基板的一部分与能量束屏蔽。 照射后，去除阻挡掩模，并将封盖材料施加到基底上。 或者，可以在照射之前施加封盖材料。 封盖材料被穿孔以允许蚀刻剂从其穿过覆盖材料下方的基底。 通过蚀刻从封盖材料的下方去除衬底的暴露部分。 然后密封封盖材料，留下基板内的密封气囊。

公开(公告)号：US20060183315A1

公开(公告)日：2006-08-17

申请号：US10906267

申请日：2005-02-11

申请人： Christos Dimitrakopoulos ,  Daniel Edelstein ,  Vincent McGahay ,  Satyanarayana Nittta ,  Kevin Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

发明人： Christos Dimitrakopoulos ,  Daniel Edelstein ,  Vincent McGahay ,  Satyanarayana Nittta ,  Kevin Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

IPC分类号： H01L21/4763

CPC分类号： H01L21/76832 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76834

摘要： A method of forming airgaps is provided where a blocking mask is applied to a substrate to shield a portion of the substrate from a beam of energy. After irradiation, the blocking mask is removed and a capping material is applied to the substrate. Alternatively, the capping material may be applied before irradiation. The capping material is perforated to allow an etchant to pass therethrough to the substrate below the capping material. The exposed portions of the substrate are removed from underneath the capping material by etching. The capping material is then sealed leaving sealed airgaps within the substrate.

摘要翻译： 提供了一种形成气隙的方法，其中将阻挡掩模施加到基板以将基板的一部分与能量束屏蔽。 照射后，去除阻挡掩模，并将封盖材料施加到基底上。 或者，可以在照射之前施加封盖材料。 封盖材料被穿孔以允许蚀刻剂从其穿过覆盖材料下方的基底。 通过蚀刻从封盖材料的下方去除衬底的暴露部分。 然后密封封盖材料，留下基板内的密封气囊。

公开(公告)号：US08415772B2

公开(公告)日：2013-04-09

申请号：US13570989

申请日：2012-08-09

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

IPC分类号： H01L23/58

CPC分类号： H01L21/28264 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

摘要翻译： 提供了防止III-V族化合物半导体的表面分解的方法。 该方法包括在III-V族化合物半导体的表面上形成厚度为从至400的硅膜。 在III-V族化合物半导体的表面上形成硅膜之后，可以在封盖/钝化的III-V化合物半导体上形成包括例如MOSFET的高性能半导体器件。 在MOSFET制造期间，可以在封盖/钝化的III-V化合物半导体上形成高k电介质，此后可以将激活的源极和漏极区域形成为III-V族化合物半导体。

公开(公告)号：US20120309153A1

公开(公告)日：2012-12-06

申请号：US13570980

申请日：2012-08-09

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

IPC分类号： H01L21/336

CPC分类号： H01L21/28264 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

公开(公告)号：US06638878B2

公开(公告)日：2003-10-28

申请号：US09969361

申请日：2001-10-02

申请人： Darryl D. Restaino ,  Jeffrey C. Hedrick ,  John A. Fitzsimmons ,  Christy S. Tyberg ,  Chih-Chien Liu ,  Shahab Siddiqui

发明人： Darryl D. Restaino ,  Jeffrey C. Hedrick ,  John A. Fitzsimmons ,  Christy S. Tyberg ,  Chih-Chien Liu ,  Shahab Siddiqui

IPC分类号： H01L21461

CPC分类号： H01L21/02304 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/31051 ,  H01L21/31058 ,  H01L21/312 ,  Y10T428/29 ,  Y10T428/31504

摘要： A method for forming a planarized dielectric layer upon a semiconductor wafer is disclosed. In an exemplary embodiment of the invention, the method includes applying an adhesion promoter to the wafer, thereby forming an adhesion promoter layer. A dielectric material is applied in a spin-on fashion upon the adhesion promoter layer at a relative humidity of less than 40% and for a thickness setting duration of less than 30 seconds. Then, the dielectric material is dried by baking without additional spinning of the semiconductor wafer.

摘要翻译： 公开了一种在半导体晶片上形成平坦化电介质层的方法。 在本发明的一个示例性实施方案中，该方法包括将粘合促进剂施加到晶片上，从而形成粘附促进剂层。 将介电材料以相对湿度小于40％并且厚度设定持续时间小于30秒以旋涂方式施加到粘合促进剂层上。 然后，通过烘烤干燥电介质材料，而不需要半导体晶片的额外纺丝。

公开(公告)号：US08349729B2

公开(公告)日：2013-01-08

申请号：US13418716

申请日：2012-03-13

申请人： Karl W. Barth ,  Ricardo A. Donaton ,  Spyridon Galis ,  Kevin S. Petrarca ,  Shahab Siddiqui

发明人： Karl W. Barth ,  Ricardo A. Donaton ,  Spyridon Galis ,  Kevin S. Petrarca ,  Shahab Siddiqui

IPC分类号： H01L21/4763

CPC分类号： H01L23/5389 ,  H01L21/76898 ,  H01L24/80 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2924/12044

摘要： Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.

摘要翻译： 第一基板和第二基板中的每一个包括具有耐扩散电介质材料如氮化硅的表面。 凹陷区域形成在耐扩散电介质材料中，并且填充有可粘结介电材料。 第一和第二基板中的金属焊盘和可接合的介质材料部分的图案可以具有镜面对称性。 第一和第二基板通过金属焊盘和可接合的介电材料部分之间的触点之间的触点进行物理接触和接合。 通过基底通孔（TSV）结构通过键合介电材料部分形成。 位于TSV结构周围的每对键合的电介质材料部分之间的界面由两个扩散电阻的介电材料层封装，使得接合界面处的金属的扩散被包含在每对键合介电材料部分内。

公开(公告)号：US20120305989A1

公开(公告)日：2012-12-06

申请号：US13570989

申请日：2012-08-09

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

IPC分类号： H01L29/78

CPC分类号： H01L21/28264 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

摘要翻译： 提供了防止III-V族化合物半导体的表面分解的方法。 该方法包括在III-V族化合物半导体的表面上形成厚度为从至400的硅膜。 在III-V族化合物半导体的表面上形成硅膜之后，可以在封盖/钝化的III-V化合物半导体上形成包括例如MOSFET的高性能半导体器件。 在MOSFET制造期间，可以在封盖/钝化的III-V化合物半导体上形成高k电介质，此后可以将激活的源极和漏极区域形成为III-V族化合物半导体。