公开(公告)号：US06864180B2

公开(公告)日：2005-03-08

申请号：US09969363

申请日：2001-10-02

申请人： Darryl D. Restaino ,  Delores Bennett ,  John A. Fitzsimmons ,  John Fritche ,  Jeffrey C. Hedrick ,  Chih-Chien Liu ,  Shahab Siddiqui ,  Christy S. Tyberg

发明人： Darryl D. Restaino ,  Delores Bennett ,  John A. Fitzsimmons ,  John Fritche ,  Jeffrey C. Hedrick ,  Chih-Chien Liu ,  Shahab Siddiqui ,  Christy S. Tyberg

IPC分类号： H01L21/311

CPC分类号： H01L21/31138 ,  H01L21/31111

摘要： A method for removing a dielectric layer formed upon a semiconductor substrate is disclosed. In an exemplary embodiment of the invention, the method includes subjecting the dielectric layer to a dry etch process and subjecting an adhesion promoter layer underneath the dielectric layer to a wet etch process.

摘要翻译： 公开了一种去除在半导体衬底上形成的电介质层的方法。 在本发明的示例性实施例中，该方法包括对介电层进行干蚀刻工艺，并对介电层下面的粘附促进剂层进行湿蚀刻工艺。

公开(公告)号：US06638878B2

公开(公告)日：2003-10-28

申请号：US09969361

申请日：2001-10-02

申请人： Darryl D. Restaino ,  Jeffrey C. Hedrick ,  John A. Fitzsimmons ,  Christy S. Tyberg ,  Chih-Chien Liu ,  Shahab Siddiqui

发明人： Darryl D. Restaino ,  Jeffrey C. Hedrick ,  John A. Fitzsimmons ,  Christy S. Tyberg ,  Chih-Chien Liu ,  Shahab Siddiqui

IPC分类号： H01L21461

CPC分类号： H01L21/02304 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/31051 ,  H01L21/31058 ,  H01L21/312 ,  Y10T428/29 ,  Y10T428/31504

摘要： A method for forming a planarized dielectric layer upon a semiconductor wafer is disclosed. In an exemplary embodiment of the invention, the method includes applying an adhesion promoter to the wafer, thereby forming an adhesion promoter layer. A dielectric material is applied in a spin-on fashion upon the adhesion promoter layer at a relative humidity of less than 40% and for a thickness setting duration of less than 30 seconds. Then, the dielectric material is dried by baking without additional spinning of the semiconductor wafer.

摘要翻译： 公开了一种在半导体晶片上形成平坦化电介质层的方法。 在本发明的一个示例性实施方案中，该方法包括将粘合促进剂施加到晶片上，从而形成粘附促进剂层。 将介电材料以相对湿度小于40％并且厚度设定持续时间小于30秒以旋涂方式施加到粘合促进剂层上。 然后，通过烘烤干燥电介质材料，而不需要半导体晶片的额外纺丝。

公开(公告)号：USRE45781E1

公开(公告)日：2015-10-27

申请号：US14176526

申请日：2014-02-10

申请人： Jeffrey C. Hedrick ,  Kang-Wook Lee ,  Kelly Malone ,  Christy S. Tyberg

发明人： Jeffrey C. Hedrick ,  Kang-Wook Lee ,  Kelly Malone ,  Christy S. Tyberg

IPC分类号： H01L21/02 ,  H01L23/532 ,  H01L21/70 ,  H01L23/52 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/22

CPC分类号： H01L21/22 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

摘要： A structure useful for electrical interconnection comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, tough, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. A method for forming the structure comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. Curing of the multilayer dielectric stack may be in a single cure step in a furnace. The application and hot plate baking of the individual layers of the multi layer dielectric stack may be accomplished in a single spin-coat tool, without being removed, to fully cure the stack until all dielectric layers have been deposited.

摘要翻译： 用于电互连的结构包括：基底; 设置在所述基板上的多个多孔介电层; 设置在第一电介质层和第二介电层之间的蚀刻停止层; 以及设置在至少一个多孔电介质层和蚀刻停止层之间的至少一个薄的，韧性的无孔介电层。 一种用于形成所述结构的方法，包括在所述衬底上形成多层介电层的多层堆叠，所述堆叠包括所述多个多孔介电层，以及在所述多层堆叠内形成多个图案化的金属导体。 多层电介质堆叠的固化可以在炉中的单一固化步骤中。 多层电介质堆叠的各层的应用和热板烘烤可以在单个旋涂工具中实现，而不被去除，以完全固化堆叠，直到所有电介质层已经沉积。

公开(公告)号：US06818285B2

公开(公告)日：2004-11-16

申请号：US10334413

申请日：2002-12-31

申请人： Jeffrey C. Hedrick ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg ,  James P. Godschalx ,  Qingshan J. Niu ,  Harry C. Silvis

发明人： Jeffrey C. Hedrick ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg ,  James P. Godschalx ,  Qingshan J. Niu ,  Harry C. Silvis

IPC分类号： B32B310

CPC分类号： H01L23/5329 ,  C08G61/00 ,  C08G61/10 ,  C08G2261/312 ,  C08G2261/46 ,  C08G2261/92 ,  C08G2650/20 ,  C08G2650/60 ,  C08L65/00 ,  C08L2203/20 ,  C08L2312/00 ,  C09D165/00 ,  H01L2924/0002 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/31504 ,  Y10T428/31855 ,  H01L2924/00

摘要： A crosslinked polyarylene material with a reduced coefficient of thermal expansion at high temperatures compared with conventional crosslinked polyarylene materials is provided. In addition, an integrated circuit article containing a crosslinked polyarylene polymer with reduced coefficient of thermal expansion at high temperatures is provided.

公开(公告)号：US08017522B2

公开(公告)日：2011-09-13

申请号：US11626550

申请日：2007-01-24

申请人： Qinghuang Lin ,  Terry A. Spooner ,  Darshan D. Gandhi ,  Christy S. Tyberg

发明人： Qinghuang Lin ,  Terry A. Spooner ,  Darshan D. Gandhi ,  Christy S. Tyberg

IPC分类号： H01L21/44 ,  H01L21/311

CPC分类号： H01L21/3105 ,  H01L21/76805 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834

摘要： A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.

摘要翻译： 提供了具有改善的低k电介质层和含电介质衬底之间的粘附强度的机械稳固的半导体结构。 特别地，本发明提供了一种结构，其包括含电介质的衬底，其具有包括化学和物理上不同于衬底的经处理的表面层的上部区域; 以及位于所述基板的经处理的表面层上的低k电介质材料。 经处理的表面层和低k电介质材料形成界面，该界面的粘合强度大于界面两侧的较弱材料的内聚强度的60％。 经处理的表面通过在形成低k电介质材料之前用光化辐射，等离子体和电子束辐射中的至少一种来处理衬底的表面而形成。

公开(公告)号：US07960808B2

公开(公告)日：2011-06-14

申请号：US11844109

申请日：2007-08-23

申请人： Geoffrey W. Burr ,  Chandrasekharan Kothandaraman ,  Chung Hon Lam ,  Xiao Hu Liu ,  Stephen M. Rossnagel ,  Christy S. Tyberg ,  Robert L. Wisnieff

发明人： Geoffrey W. Burr ,  Chandrasekharan Kothandaraman ,  Chung Hon Lam ,  Xiao Hu Liu ,  Stephen M. Rossnagel ,  Christy S. Tyberg ,  Robert L. Wisnieff

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.

摘要翻译： 集成电路中的可逆熔丝结构通过实现具有短路相变材料的熔断电池获得，所述相变材料与能够使电流通过相变材料线（熔丝电池）的通孔和线结构相接触。 电流通过熔丝电池，以便通过将结晶状态的相变材料加热至熔点，从而将材料从较小电阻的材料转变为更电阻的材料，然后快速将材料淬火成非晶状态。 可逆编程通过使较低电流通过熔丝电池来实现，以将高电阻率无定形材料转换成较低电阻率的晶体材料。 集成适当的感测电路以读取存储在熔丝中的信息，其中所述感测电路用于启用或禁用电路。

公开(公告)号：US07598169B2

公开(公告)日：2009-10-06

申请号：US11677100

申请日：2007-02-21

申请人： Qinghuang Lin ,  Elbert E. Huang ,  Christy S. Tyberg ,  Ronald A. DellaGuardia

发明人： Qinghuang Lin ,  Elbert E. Huang ,  Christy S. Tyberg ,  Ronald A. DellaGuardia

IPC分类号： H01L21/4763

CPC分类号： H01L21/31127 ,  H01L21/02063 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826

摘要： A method to fabricate interconnect structures that are part of integrated circuits and microelectronic devices by utilization of an irradiation to remove and clean a sacrificial material used therein is described. The advantages of utilizing the irradiation to remove the sacrificial material include reduced damage to interlayer dielectric layers that result in enhanced device performance and/or increased reliability.

摘要翻译： 描述了通过利用照射去除和清洁其中使用的牺牲材料来制造作为集成电路和微电子器件的一部分的互连结构的方法。 利用照射去除牺牲材料的优点包括降低对层间电介质层的损伤，导致增强的器件性能和/或增加的可靠性。

公开(公告)号：US20080173984A1

公开(公告)日：2008-07-24

申请号：US11626550

申请日：2007-01-24

申请人： Qinghuang Lin ,  Terry A. Spooner ,  Darshan D. Gandhi ,  Christy S. Tyberg

发明人： Qinghuang Lin ,  Terry A. Spooner ,  Darshan D. Gandhi ,  Christy S. Tyberg

IPC分类号： H01L23/58 ,  H01L21/31

CPC分类号： H01L21/3105 ,  H01L21/76805 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834

摘要： A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.

摘要翻译： 提供了具有改善的低k电介质层和含电介质衬底之间的粘附强度的机械稳固的半导体结构。 特别地，本发明提供了一种结构，其包括含电介质的衬底，其具有包括化学和物理上不同于衬底的经处理的表面层的上部区域; 以及位于所述基板的经处理的表面层上的低k电介质材料。 经处理的表面层和低k电介质材料形成界面，该界面的粘合强度大于界面两侧的较弱材料的内聚强度的60％。 经处理的表面通过在形成低k电介质材料之前用光化辐射，等离子体和电子束辐射中的至少一种来处理衬底的表面而形成。

公开(公告)号：US20110207286A1

公开(公告)日：2011-08-25

申请号：US13100456

申请日：2011-05-04

申请人： Geoffrey W. Burr ,  Chandrasekharan Kothandaraman ,  Chung Hon Lam ,  Xiao Hu Liu ,  Stephen M. Rossnagel ,  Christy S. Tyberg ,  Robert L. Wisnieff

发明人： Geoffrey W. Burr ,  Chandrasekharan Kothandaraman ,  Chung Hon Lam ,  Xiao Hu Liu ,  Stephen M. Rossnagel ,  Christy S. Tyberg ,  Robert L. Wisnieff

IPC分类号： H01L21/768

CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.

摘要翻译： 集成电路中的可逆熔丝结构通过实现具有短路相变材料的熔断电池获得，所述相变材料与能够使电流通过相变材料线（熔丝电池）的通孔和线结构相接触。 电流通过熔丝电池，以便通过将结晶状态的相变材料加热至熔点，从而将材料从较小电阻的材料转变为更电阻的材料，然后快速将材料淬火成非晶状态。 可逆编程通过使较低电流通过熔丝电池来实现，以将高电阻率无定形材料转换成较低电阻率的晶体材料。 集成适当的感测电路以读取存储在熔丝中的信息，其中所述感测电路用于启用或禁用电路。

公开(公告)号：US20100006850A1

公开(公告)日：2010-01-14

申请号：US12561827

申请日：2009-09-17

申请人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

发明人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

IPC分类号： H01L23/522 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L23/5226 ,  H01L23/53271 ,  H01L27/124 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

摘要翻译： 本发明提供了用于在线路后端（BEOL）互连结构中并入薄膜晶体管的结构和制造工艺。 所描述的结构和制造工艺与BEOL互连结构的处理要求相兼容。 结构和制造工艺利用已经并入到互连布线层中的现有处理步骤和材料，以便降低与在这些层级中引入薄膜晶体管相关联的附加成本。 与现有技术的3D集成方法相比，该结构能够实现多层次的垂直（3D）集成，具有改进的可制造性和可靠性。