公开(公告)号：US11800717B2

公开(公告)日：2023-10-24

申请号：US17661659

申请日：2022-05-02

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  David A. Daycock ,  Yoshiaki Fukuzumi ,  Albert Fayrushin ,  Richard J. Hill ,  Chandra S. Tiwari ,  Jun Fujiki

IPC: H01L21/76 ,  H01L29/06 ,  H10B43/27 ,  H01L21/762

CPC classification number: H10B43/27 ,  H01L21/76224 ,  H01L29/0649

Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.

公开(公告)号：US11616079B2

公开(公告)日：2023-03-28

申请号：US17525817

申请日：2021-11-12

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Augusto Benvenuti ,  Haitao Liu ,  Xin Lan

IPC: H01L27/11582 ,  H01L29/10 ,  H01L27/11573 ,  H01L29/51 ,  H01L27/11565

Abstract: Some embodiments include a pillar which contains semiconductor material, and which extends primarily along a first direction. A cross-section through the pillar along a second direction orthogonal to the first direction is through the semiconductor material and includes a lateral periphery of the pillar configured as three-sided shape. Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. The first levels include conductive structures and the second levels are insulative. Channel-material-pillars extend through the vertical stack. Each of the channel-material-pillars has a top-down cross-section which includes a lateral periphery configured as three-sided shape of an equilateral triangle with rounded vertices.

公开(公告)号：US20220238548A1

公开(公告)日：2022-07-28

申请号：US17158888

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Litao Yang ,  Albert Fayrushin ,  Naveen Kaushik ,  Jian Li ,  Collin Howder

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative and conductive structures arranged in tiers. At least one pillar, comprising a channel material, extends through the stack structure. A source region, below the stack structure, comprises a doped material with vertical extensions that protrude to an interface with the channel material at an elevation proximate at least one source-side GIDL region. Slit structures extend through the stack structure to divide the structure into blocks of pillar arrays. A series of spaced, discrete pedestal structures are included along a base of the slit structures. Forming the microelectronic device structure may include forming a lateral opening through cell materials of the pillar, vertically recessing the channel material, and laterally recessing other material(s) of the pillar before forming the doped material in the broadened recesses. Additional microelectronic devices, related methods, and electronic systems are also disclosed.

公开(公告)号：US20220068969A1

公开(公告)日：2022-03-03

申请号：US17525817

申请日：2021-11-12

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Augusto Benvenuti ,  Haitao Liu ,  Xin Lan

IPC: H01L27/11582 ,  H01L29/10 ,  H01L27/11573 ,  H01L29/51 ,  H01L27/11565

Abstract: Some embodiments include a pillar which contains semiconductor material, and which extends primarily along a rust direction. A cross-section through the pillar along a second direction orthogonal to the first direction is through the semiconductor material and includes a lateral periphery of the pillar configured as three-sided shape. Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. The first levels include conductive structures and the second levels ae insulative. Channel-material-pillars extend through the vertical stack. Each of the channel-material-pillars has a top-down cross-section which includes a lateral periphery configured as three-sided shape of an equilateral triangle with rounded vertices.

公开(公告)号：US20220068955A1

公开(公告)日：2022-03-03

申请号：US17007951

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  David A. Daycock ,  Yoshiaki Fukuzumi ,  Albert Fayrushin ,  Richard J. Hill ,  Chandra S. Tiwari ,  Jun Fujiki

IPC: H01L27/11582 ,  H01L21/762 ,  H01L29/06

Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.

公开(公告)号：US20210384201A1

公开(公告)日：2021-12-09

申请号：US17445867

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Andrew Bicksler ,  Marc Aoulaiche ,  Albert Fayrushin

IPC: H01L27/1157 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/24 ,  G06F3/06 ,  G11C16/34 ,  G11C16/08

Abstract: Back gates and related apparatuses, systems, and methods are disclosed. An apparatus includes a channel material including a first side and a second side opposite the first side. The apparatus also includes word lines comprising electrically conductive material spaced along the first side of the channel material. The apparatus further includes a back gate comprising electrically conductive material proximate to the second side of the channel material. A method includes biasing a bit line and a word line associated with a memory cell according to a memory operation, and biasing the back gate while biasing the bit line and the word line.

公开(公告)号：US11127751B2

公开(公告)日：2021-09-21

申请号：US16735098

申请日：2020-01-06

Applicant: Micron Technology, Inc.

Inventor： Andrew Bicksler ,  Marc Aoulaiche ,  Albert Fayrushin

IPC: H01L27/1157 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/24 ,  G06F3/06 ,  G11C16/34 ,  G11C16/08

Abstract: Back gates and related apparatuses, systems, and methods are disclosed. An apparatus includes a channel material including a first side and a second side opposite the first side. The apparatus also includes word lines comprising electrically conductive material spaced along the first side of the channel material. The apparatus further includes a back gate comprising electrically conductive material proximate to the second side of the channel material. A method includes biasing a bit line and a word line associated with a memory cell according to a memory operation, and biasing the back gate while biasing the bit line and the word line.

公开(公告)号：US20210151464A1

公开(公告)日：2021-05-20

申请号：US17140494

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Haitao Liu ,  Mojtaba Asadirad

IPC: H01L27/11582 ,  H01L29/10 ,  H01L23/522 ,  H01L23/528 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, and a channel structure within an opening vertically extending through the stack and comprising a first semiconductor material having a first band gap. The semiconductor device also comprises a conductive plug structure within the opening and in direct contact with the channel region, and a band offset structure within the opening and in direct physical contact with the channel structure and the conductive plug structure. The band offset structure comprises a second semiconductor material having a second band gap different than the first band gap. The semiconductor device further comprises a conductive line structure electrically coupled to the conductive plug structure. A method of forming a semiconductor device and an electronic system are also described.

公开(公告)号：US10923493B2

公开(公告)日：2021-02-16

申请号：US16123538

申请日：2018-09-06

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Haitao Liu ,  Mojtaba Asadirad

IPC: H01L27/11582 ,  H01L29/10 ,  H01L23/522 ,  H01L23/528 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14

Abstract: A semiconductor device comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, and a channel structure within an opening vertically extending through the stack and comprising a first semiconductor material having a first band gap. The semiconductor device also comprises a conductive plug structure within the opening and in direct contact with the channel region, and a band offset structure within the opening and in direct physical contact with the channel structure and the conductive plug structure. The band offset structure comprises a second semiconductor material having a second band gap different than the first band gap. The semiconductor device further comprises a conductive line structure electrically coupled to the conductive plug structure. A method of forming a semiconductor device and an electronic system are also described.

公开(公告)号：US20200143884A1

公开(公告)日：2020-05-07

申请号：US16183414

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Augusto Benvenuti ,  Akira Goda ,  Luca Laurin ,  Haitao Liu

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/16 ,  G11C16/04

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.