公开(公告)号：US11672118B2

公开(公告)日：2023-06-06

申请号：US17013047

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Byeung Chul Kim ,  Francois H. Fabreguette ,  Chris M. Carlson ,  Michael E. Koltonski ,  Shane J. Trapp

IPC: H01L27/11582

CPC classification number: H01L27/11582

Abstract: An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US20210335817A1

公开(公告)日：2021-10-28

申请号：US17369605

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill ,  Byeung Chul Kim ,  Akira Goda

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/792 ,  H01L21/28 ,  H01L29/49 ,  H01L29/788

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US11107830B2

公开(公告)日：2021-08-31

申请号：US16548267

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H Fabreguette ,  Richard J. Hill ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788 ,  H01L21/02 ,  H01L29/792

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US11037956B2

公开(公告)日：2021-06-15

申请号：US16988548

申请日：2020-08-07

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/02 ,  G11C16/08

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210143171A1

公开(公告)日：2021-05-13

申请号：US16681200

申请日：2019-11-12

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. Memory cells are along the conductive levels. The conductive levels have control gate regions which include a first vertical thickness, have routing regions which include a second vertical thickness that is less than the first vertical thickness, and have tapered transition regions between the first vertical thickness and the second vertical thickness. Charge-blocking material is adjacent to the control gate regions. Charge-storage material is adjacent to the charge-blocking material. Dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the vertical stack and is adjacent to the dielectric material. The memory cells include the control gate regions, and include regions of the charge-blocking material, the charge-storage material, the dielectric material and the channel material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10943907B2

公开(公告)日：2021-03-09

申请号：US16869316

申请日：2020-05-07

Applicant: Micron Technology, Inc.

Inventor： Cornel Bozdog ,  Abhilasha Bhardwaj ,  Byeung Chul Kim ,  Michael E. Koltonski ,  Gurtej S. Sandhu ,  Matthew Thorum

IPC: H01L21/108 ,  H01L23/528 ,  H01L23/522 ,  H01L21/822 ,  H01L27/108

Abstract: Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

公开(公告)号：US10930548B2

公开(公告)日：2021-02-23

申请号：US16250778

申请日：2019-01-17

Applicant: Micron Technology, Inc.

Inventor： Shane J. Trapp ,  Timothy A. Quick ,  Byeung Chul Kim

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3065

Abstract: A method of forming an apparatus comprises conformally forming a spacer material over and between structures overlying a base structure. A liner material is conformally formed on the spacer material. The spacer material is selectively etchable relative to the liner material through exposure to at least one etchant. Portions of the liner material and the spacer material overlying upper surfaces of the structures and upper surfaces of the base structure horizontally between the structures are selectively removed to form spacer structures flanking side surfaces of the structures. An apparatus and an electronic system are also described.

公开(公告)号：US10770465B1

公开(公告)日：2020-09-08

申请号：US16399348

申请日：2019-04-30

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Richard J. Hill ,  John A. Smythe ,  Gurtej S. Sandhu

IPC: H01L27/108

Abstract: A method used in forming integrated circuitry comprises forming a substrate comprising a conductive line structure comprising opposing longitudinal sides individually comprising a sacrificial material that is laterally between insulator material. The sacrificial material comprises metal oxide. At least some of the sacrificial material is removed to form an upwardly-open void space laterally between the insulator material on the opposing longitudinal sides of the conductive line structure. The void space is covered with insulating material to leave a sealed void space beneath the insulating material on the opposing longitudinal sides of the conductive line structure. Other embodiments are disclosed.

公开(公告)号：US20200266197A1

公开(公告)日：2020-08-20

申请号：US16869316

申请日：2020-05-07

Applicant: Micron Technology, Inc.

Inventor： Cornel Bozdog ,  Abhilasha Bhardwaj ,  Byeung Chul Kim ,  Michael E. Koltonski ,  Gurtej S. Sandhu ,  Matthew Thorum

IPC: H01L27/108 ,  H01L21/822 ,  H01L23/522 ,  H01L23/528

Abstract: Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

公开(公告)号：US20200235004A1

公开(公告)日：2020-07-23

申请号：US16250778

申请日：2019-01-17

Applicant: Micron Technology, Inc.

Inventor： Shane J. Trapp ,  Timothy A. Quick ,  Byeung Chul Kim

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/02

Abstract: A method of forming an apparatus comprises conformally forming a spacer material over and between structures overlying a base structure. A liner material is conformally formed on the spacer material. The spacer material is selectively etchable relative to the liner material through exposure to at least one etchant. Portions of the liner material and the spacer material overlying upper surfaces of the structures and upper surfaces of the base structure horizontally between the structures are selectively removed to form spacer structures flanking side surfaces of the structures. An apparatus and an electronic system are also described.