公开(公告)号：US20210111184A1

公开(公告)日：2021-04-15

申请号：US16653062

申请日：2019-10-15

Applicant: Micron Technology, Inc.

Inventor： Cole Smith ,  Ramey M. Abdelrahaman ,  Silvia Borsari ,  Chris M. Carlson ,  David Daycock ,  Matthew J. King ,  Jin Lu

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11556

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.

公开(公告)号：US10937802B2

公开(公告)日：2021-03-02

申请号：US16452292

申请日：2019-06-25

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/51 ,  H01L29/423

Abstract: Various embodiments include methods and apparatus having a number of charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric region, the blocking dielectric region located on a charge trap region of the charge trap structure. At least a portion of the gate can be separated by a void from a region which the charge trap structure is directly disposed. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US10854747B2

公开(公告)日：2020-12-01

申请号：US16412710

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  Hung-Wei Liu ,  Jie Li ,  Dimitrios Pavlopoulos

IPC: H01L29/16 ,  H01L29/20 ,  H01L29/10 ,  H01L21/321 ,  H01L29/78 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/02 ,  H01L29/788 ,  H01L29/792

Abstract: Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20200266203A1

公开(公告)日：2020-08-20

申请号：US16277311

申请日：2019-02-15

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Chris M. Carlson ,  Collin Howder

IPC: H01L27/11556 ,  G11C8/14 ,  G11C16/04 ,  G06F3/06 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11558 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.

公开(公告)号：US20190371815A1

公开(公告)日：2019-12-05

申请号：US16437781

申请日：2019-06-11

Applicant: Micron Technology, Inc.

Inventor： Zhiqiang Xie ,  Chris M. Carlson ,  Justin B. Dorhout ,  Anish A. Khandekar ,  Greg Light ,  Ryan Meyer ,  Kunal R. Parekh ,  Dimitrios Pavlopoulos ,  Kunal Shrotri

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/02

Abstract: An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers have terminal ends corresponding to control-gate regions of individual memory cells. The control-gate regions individually comprise part of a wordline in individual of the wordline tiers. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions. Charge-storage material of the individual memory cells extends elevationally along individual of the charge-blocking regions. Channel material extends elevationally along the vertical stack. Insulative charge-passage material is laterally between the channel material and the charge-storage material. Elevationally-extending walls laterally separate immediately-laterally-adjacent of the wordlines. The walls comprise laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material. The silicon-containing material comprises at least 30 atomic percent of at least one of elemental-form silicon or a silicon-containing alloy. Other aspects, including method, are also disclosed.

公开(公告)号：US20190312058A1

公开(公告)日：2019-10-10

申请号：US16452292

申请日：2019-06-25

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L27/11582 ,  H01L29/51 ,  H01L29/423 ,  H01L21/28 ,  H01L27/1157

Abstract: Various embodiments include methods and apparatus having a number of charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric region, the blocking dielectric region located on a charge trap region of the charge trap structure. At least a portion of the gate can be separated by a void from a region which the charge trap structure is directly disposed. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20190280122A1

公开(公告)日：2019-09-12

申请号：US16412710

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  Hung-Wei Liu ,  Jie Li ,  Dimitrios Pavlopoulos

IPC: H01L29/78 ,  H01L27/11582 ,  H01L29/788 ,  H01L29/792 ,  H01L21/02 ,  H01L27/1157 ,  H01L27/11524 ,  H01L29/20 ,  H01L29/16 ,  H01L29/10 ,  H01L27/11556

Abstract: Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20170323979A1

公开(公告)日：2017-11-09

申请号：US15149553

申请日：2016-05-09

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L29/792 ,  H01L29/26 ,  H01L27/1157 ,  H01L29/788 ,  H01L27/11524

CPC classification number: H01L29/40117 ,  H01L29/40114

Abstract: Some embodiments include an integrated structure having a gallium-containing material between a charge-storage region and a semiconductor-containing channel region. Some embodiments include an integrated structure having a charge-storage region under a conductive gate, a tunneling region under the charge-storage region, and a semiconductor-containing channel region under the tunneling region. The tunneling region includes at least one dielectric material directly adjacent a gallium-containing material. Some embodiments include an integrated structure having a charge-trapping region under a conductive gate, a first oxide under the charge-storage region, a gallium-containing material under the first oxide, a second oxide under the gallium-containing material, and a semiconductor-containing channel region under the second oxide.

公开(公告)号：US11923407B2

公开(公告)日：2024-03-05

申请号：US17739621

申请日：2022-05-09

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L29/06 ,  H01L21/764 ,  H10B41/27 ,  H10B41/30 ,  H10B43/27 ,  H10B43/30 ,  G11C16/04 ,  G11C16/06

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H10B41/27 ,  H10B41/30 ,  H10B43/27 ,  H10B43/30 ,  G11C16/0483 ,  G11C16/06

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a channel to conduct current, the channel including a first channel portion and a second channel portion, a first memory cell structure located between a first gate and the first channel portion, a second memory cell structure located between a second gate and the second channel portion, and a void located between the first and second gates and between the first and second memory cell structures.

公开(公告)号：US11765903B2

公开(公告)日：2023-09-19

申请号：US17748641

申请日：2022-05-19

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L27/11582 ,  H01L21/28 ,  H01L29/423 ,  H10B43/27

CPC classification number: H10B43/27 ,  H01L29/40117 ,  H01L29/4234

Abstract: Various embodiments, disclosed herein, include methods and apparatus having charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, material of the dielectric barrier of each of the charge trap structures may have a dielectric constant greater than that of aluminum oxide. Additional apparatus, systems, and methods are disclosed.