公开(公告)号：US10403340B2

公开(公告)日：2019-09-03

申请号：US15890943

申请日：2018-02-07

Applicant: Micron Technology, Inc.

Inventor： Yoshiya Komatsu ,  Kazutaka Miyano ,  Atsuko Momma

IPC: G11C7/22 ,  G11C8/10 ,  H03L7/08

Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.

公开(公告)号：US20160322964A1

公开(公告)日：2016-11-03

申请号：US14698550

申请日：2015-04-28

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano

IPC: H03K5/135 ,  H03K3/037 ,  H03L7/081 ,  H03K5/14

CPC classification number: H03K5/135 ,  G11C7/106 ,  G11C7/1066 ,  G11C2207/2272 ,  H03K3/037 ,  H03K5/14 ,  H03L7/0812

Abstract: Methods and apparatus including a latency control circuit are described. An example apparatus includes a delay line circuit configured to delay a clock signal, and a latch control circuit configured to receive the clock signal and the delayed clock signal. The latch control circuit is configured to provide first control signals based on a count associated with the first clock signal. The latch control circuit is further configured to provide second control signals based on the count associated with the first clock signal. The second clock signals are delayed relative to the first clock signals by an amount substantially equal to a delay between the clock signal and the delayed clock signal. The example apparatus further includes a latch circuit configured to latch an input signal responsive to the first control signals. The latch circuit is further configured to provide the latched signal to an output responsive to the second control signals.

Abstract translation: 描述包括等待时间控制电路的方法和装置。 一种示例性装置包括：延迟线电路，被配置为延迟时钟信号;锁存器控制电路，被配置为接收时钟信号和延迟的时钟信号。 锁存器控制电路被配置为基于与第一时钟信号相关联的计数来提供第一控制信号。 锁存控制电路还被配置为基于与第一时钟信号相关联的计数来提供第二控制信号。 第二时钟信号相对于第一时钟信号被延迟大致等于时钟信号和延迟的时钟信号之间的延迟的量。 该示例设备还包括锁存电路，其被配置为响应于第一控制信号锁存输入信号。 锁存电路还被配置为响应于第二控制信号向锁存的信号提供锁存信号。

公开(公告)号：US20150043299A1

公开(公告)日：2015-02-12

申请号：US14341601

申请日：2014-07-25

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Hiroki Fujisawa

IPC: G11C11/4074 ,  G11C11/408 ,  G11C11/4076

CPC classification number: G11C11/4074 ,  G11C7/1057 ,  G11C7/222 ,  G11C2207/2227

Abstract: A device includes an output circuit, a DLL (Delay Locked Loop) circuit including a first delay line receiving a first clock signal and outputting, in response to receiving the clock signal, a second clock signal supplied to the output circuit, and an ODT (On Die Termination) circuit receiving an ODT activation signal and outputting, in response to receiving the ODT activation signal, an ODT output signal supplied to the output circuit to set the output circuit in a resistance termination state, and the ODT circuit including a second delay line configured to be set by the DLL circuit in an equivalent delay amount that is equivalent to a delay amount of the first delay line, the ODT output signal being, in a first time-period during which the ODT activation signal is in an active state, generated by being conveyed via the second delay line in which the equivalent delay amount has been set.

Abstract translation: 一种设备包括输出电路，DLL（延迟锁定环路）电路，包括接收第一时钟信号的第一延迟线，并且响应于接收到时钟信号而输出提供给输出电路的第二时钟信号，以及ODT 接通ODT激活信号，并且响应于接收到ODT激活信号而输出提供给输出电路的ODT输出信号，以将输出电路设置为电阻终止状态，并且包括第二延迟的ODT电路 线路被配置为由等效延迟量等效于第一延迟线的延迟量由DLL电路设置，ODT输出信号在ODT激活信号处于活动状态的第一时间段期间 通过被设置了等效延迟量的第二延迟线传送而产生。