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    Restoring memory cell threshold voltages
    31.
    发明授权
    Restoring memory cell threshold voltages 有权

    公开(公告)号：US11508437B2

    公开(公告)日：2022-11-22

    申请号：US17196638

    申请日：2021-03-09

    Applicant: Micron Technology, Inc.

    Inventor： Lingming Yang ,  Nevil Gajera ,  Karthik Sarpatwari

    IPC: G11C7/00 ,  G11C13/00

    Abstract: Methods, systems, and devices for restoring memory cell threshold voltages are described. A memory device may perform a write operation on a memory cell during which a logic state is stored at the memory cell. Upon detecting satisfaction of a condition, the memory device may perform a read refresh operation on the memory cell during which the threshold voltage of the memory cell may be modified. In some cases, the duration of the read refresh operation may be longer than the duration of a read operation performed by the memory device on the memory cell or on a different memory cell.

    PERFORMING REFRESH OPERATIONS ON MEMORY CELLS
    32.
    发明申请
    PERFORMING REFRESH OPERATIONS ON MEMORY CELLS 有权

    公开(公告)号：US20220246202A1

    公开(公告)日：2022-08-04

    申请号：US17167922

    申请日：2021-02-04

    Applicant: Micron Technology, Inc.

    Inventor： Karthik Sarpatwari ,  Lingming Yang ,  Nevil N. Gajera ,  John Christopher M. Sancon

    IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4091

    Abstract: The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. A memory can include a group of memory cells and one or more additional memory cells whose data state is indicative of whether to refresh the group of memory cells. Circuitry is configured to apply a first voltage pulse to the group of memory cells to sense a data state of the memory cells of the group, apply, while the first voltage pulse is applied to the group of memory cells, a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense a data state of the one or more additional memory cells, and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.

    Drift aware read operations
    34.
    发明授权
    Drift aware read operations 有权

    公开(公告)号：US12176029B2

    公开(公告)日：2024-12-24

    申请号：US17980382

    申请日：2022-11-03

    Applicant: Micron Technology, Inc.

    Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Lingming Yang ,  John F. Schreck

    IPC: G11C7/10 ,  G11C13/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

    Abstract: Systems, methods and apparatus to read target memory cells having an associated reference memory cell configured to be representative of drift or changes in the threshold voltages of the target memory cells. The reference cell is programmed to a predetermined threshold level when the target cells are programmed to store data. In response to a command to read the target memory cells, estimation of a drift of the threshold voltage of the reference is performed in parallel with applying an initial voltage pulse to read the target cells. Based on a result of the drift estimation, voltage pulses used to read the target cells can be modified and/or added to account for the drift estimated using the reference cell.

    Instant write scheme with delayed parity/raid
    36.
    发明授权
    Instant write scheme with delayed parity/raid 有权

    公开(公告)号：US12019516B2

    公开(公告)日：2024-06-25

    申请号：US17894886

    申请日：2022-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Lingming Yang ,  Amitava Majumdar ,  Sandeep Krishna Thirumala ,  Nevil Gajera

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0689 ,  G06F11/1096

    Abstract: Provided is a memory system comprising a plurality of memory channels each having a parity bit, a redundant array of independent devices (RAID) parity channel, and a controller of the memory system. The controller is configured to receive a block of data for storage in the memory channels and determine at least one of (i) when a data traffic demand on the memory channels is high and (ii) when a data traffic demand on the memory channels is low. Upon determining the data traffic demand is low, writing the block of data for storage in the memory channels and concurrently updating the parity bits and the RAID parity channel for the stored block of data. Upon determining the data traffic demand is high, only writing the data for storage in the memory channels.

    DATA CORRECTION SCHEME WITH REDUCED DEVICE OVERHEAD
    37.
    发明公开
    DATA CORRECTION SCHEME WITH REDUCED DEVICE OVERHEAD 审中-公开

    公开(公告)号：US20240004756A1

    公开(公告)日：2024-01-04

    申请号：US18211881

    申请日：2023-06-20

    Applicant: Micron technology, Inc.

    Inventor： Joseph M. McCrate ,  Marco Sforzin ,  Paolo Amato ,  Lingming Yang ,  Nevil N. Gajera

    IPC: G06F11/10 ,  G06F11/07

    CPC classification number: G06F11/1068 ,  G06F11/0772

    Abstract: Methods, systems, and devices for data correction schemes with reduced device overhead are described. A memory system may include a set of memory devices storing data and check codes associated with the data. The memory system may additionally include a single parity device storing parity information associated with the data. During a read operation of a set of data, a controller of the memory system may detect an error in data associated with a first check code, the data including two or more subsets of the set of data received from two or more corresponding memory devices. The controller may generate candidate data corresponding to one of the two or more subsets using the parity information and remaining subsets of the set of data. Then the controller may determine whether the candidate data is correct by comparing the first check code with a check value generated using the candidate data.

    ADDRESS MAPPING FOR IMPROVED MEMORY RELIABILITY
    38.
    发明公开
    ADDRESS MAPPING FOR IMPROVED MEMORY RELIABILITY 审中-公开

    公开(公告)号：US20230238049A1

    公开(公告)日：2023-07-27

    申请号：US17844450

    申请日：2022-06-20

    Applicant: Micron Technology, Inc.

    Inventor： Sandeep Krishna Thirumala ,  Amitava Majumdar ,  Lingming Yang ,  Nevil Gajera

    IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4096 ,  G06F12/02 ,  G06F11/10

    CPC classification number: G11C11/4085 ,  G11C11/4094 ,  G11C11/4096 ,  G06F12/0238 ,  G06F11/1068 ,  G06F2212/7201

    Abstract: Provided is a memory system including a memory module bank comprising a plurality of memory cell arrays, each memory cell array comprising a plurality of memory cells arranged in wordlines and bitlines and a memory controller configured to receive from a central processing unit (CPU) a data byte to be stored in a wordline of the memory module bank. Also included is a logical-to-physical address mapping block (L2P AMB) configured to map a logical bitline address of the data byte to a physical bitline address of a first memory cell array of the plurality of memory cell arrays, wherein a plurality of logical bitline addresses of the data byte are shuffled to different physical bitline memory addresses of the first memory cell array. Each respective memory cell array of the plurality stores a respective bit value, corresponding to a common logical bitline address, to a different respective physical bitline in each different respective memory cell array of the plurality.

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