公开(公告)号：US20230141713A1

公开(公告)日：2023-05-11

申请号：US16976690

申请日：2020-03-03

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C29/46 ,  G11C29/12 ,  G11C29/42

CPC classification number: G11C29/46 ,  G11C29/42 ,  G11C29/1201

Abstract: Methods, systems, and devices related to counter-based sense amplifier method for memory cells are described. The counter-based read algorithm may comprise the following phases:

storing in a counter associated to an array of memory cells the value of the number of bits having a predetermined logic value of the data bits stored in the memory array;
reading from said counter the value corresponding to the number of bits having the predetermined logic value;
reading the data stored in the array of memory cells by applying a ramp of biasing voltages;
counting the number of bits having the predetermined logic value during the data reading phase;
stopping the data reading phase when the number of bits having the predetermined logic value is equal to the value stored in said counter.

公开(公告)号：US20220366957A1

公开(公告)日：2022-11-17

申请号：US17826979

申请日：2022-05-27

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto

IPC: G11C11/22

Abstract: Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The self-referencing memory device may be configured to determine a logic state stored in a memory cell based on a state signal generated using the ferroelectric memory cell and a reference signal generated using the ferroelectric memory cell. The biasing of the plate line of the ferroelectric memory cell may be used to generate the voltage need to generate the state signal during a first time period of an access operation and to generate the reference signal during a second time period of the access operation. Procedures and operations related to a self-referencing memory device are described.

公开(公告)号：US20220343979A1

公开(公告)日：2022-10-27

申请号：US16975619

申请日：2020-03-24

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Efrem Bolandrina ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

Abstract: A memory device with single transistor drivers and methods to operate the memory device are described. In some embodiments, the memory device may comprise memory cells at cross points of access lines of a memory array, a first even single transistor driver configured to drive a first even access line to a discharging voltage during an IDLE phase, to drive the first even access line to a floating voltage during an ACTIVE phase, and to drive the first even access line to a read/program voltage during a PULSE phase, and a first odd single transistor driver configured to drive a first odd access line, the first odd access line physically adjacent to the first even access line, to the discharging voltage during the IDLE phase, to drive the first odd access line to the floating voltage during the ACTIVE phase, and to drive the first odd access line to a shielding voltage during the PULSE phase.

公开(公告)号：US20220172778A1

公开(公告)日：2022-06-02

申请号：US17108763

申请日：2020-12-01

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Jeffrey E. Koelling ,  Hari Giduturi ,  Riccardo Muzzetto ,  Corrado Villa

IPC: G11C13/00

Abstract: Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.

公开(公告)号：US20210398581A1

公开(公告)日：2021-12-23

申请号：US16908299

申请日：2020-06-22

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C11/22 ,  G06F11/07

Abstract: Methods, systems, and devices for a read algorithm for a memory device are described. When performing a read operation, the memory device may access a memory cell to retrieve a value stored by the memory cell. The memory device may compare a set of reference voltages with a signal output by the memory cell based on accessing the memory cell. Thus, the memory device may determine a set of candidate values stored by the memory cell, where each candidate value is associated with one of the reference voltages. The memory device may determine and output the value stored by the memory cell based on determining the set of candidate values. In some cases, the memory device may determine the value stored by the memory cell based on performing an error control operation on each of the set of candidate values to detect a quantity of errors within each candidate value.

公开(公告)号：US20210319820A1

公开(公告)日：2021-10-14

申请号：US17241889

申请日：2021-04-27

Applicant: Micron Technology, Inc

Inventor： Umberto Di Vincenzo ,  Ferdinando Bedeschi ,  Riccardo Muzzetto

IPC: G11C11/22

Abstract: Methods and devices for reading a memory cell using a sense amplifier with split capacitors is described. The sense amplifier may include a first capacitor and a second capacitor that may be configured to provide a larger capacitance during certain portions of a read operation and a lower capacitance during other portions of the read operation. In some cases, the first capacitor and the second capacitor are configured to be coupled in parallel between a signal node and a voltage source during a first portion of the read operation to provide a higher capacitance. The first capacitor may be decoupled from the second capacitor during a second portion of the read operation to provide a lower capacitance during the second portion.

公开(公告)号：US20210280223A1

公开(公告)日：2021-09-09

申请号：US17075502

申请日：2020-10-20

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C7/10 ,  G11C7/06 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42

Abstract: The present invention relates to a method of operating memory cells, comprising reading a previous user data from the memory cells; writing a new user data and merging the new user data with the previous user data into write registers; generating mask register information, and wherein the mask register information indicates bits of the previous user data stored in the memory cells to be switched or not to be switched in their logic values; counting numbers of a first logic value and a second logic value to be written using the mask register information, respectively; storing the numbers of the first logic value and the second logic value into a first counter and a second counter, respectively; and applying a programming pulse to the memory cells according to the mask register information.

公开(公告)号：US20210233578A1

公开(公告)日：2021-07-29

申请号：US17165529

申请日：2021-02-02

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Efrem Bolandrina ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C11/22

Abstract: Methods, systems, and devices for sensing techniques for a memory cell are described to enable a latch to sense a logic state of a memory cell. A transistor coupled with a memory cell may boost a first voltage associated with the memory cell to a second voltage via one or more parasitic capacitances of the transistor. The second voltage may be developed on a first node of a sense component, and the second voltage may be shifted to a third voltage at a first node of the sense component by applying a voltage to a shift node coupled with a capacitor of the sense component. Similar boosting and shifting operations may be performed to develop a reference voltage on a second node of the sense component. The sense component may sense the state of the memory cell by comparing with the reference voltage.

公开(公告)号：US20210217471A1

公开(公告)日：2021-07-15

申请号：US16771657

申请日：2019-12-03

Applicant: Micron Technology , Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C13/00

Abstract: The present disclosure relates to a method for reading memory cells, comprising the steps of applying a first read voltage to a plurality of memory cells, detecting first threshold voltages exhibited by the plurality of memory cells in response to application of the first read voltage, based on the first threshold voltages, associating a first logic state to one or more cells of the plurality of memory cells, applying a second read voltage to the plurality of memory cells, wherein the second read voltage has the same polarity of the first read voltage and a higher magnitude than an expected highest threshold voltage of memory cells in the first logic state, detecting second threshold voltages exhibited by the plurality of memory cells in response to application of the second read voltage, based on the second threshold voltages, associating a second logic state to one or more cells of the plurality of memory cells, applying a third read voltage to the plurality of memory cells, wherein the third read voltage has the same polarity of the first and second read voltages and is applied at least to a group of memory cells that, during the application the second read voltage, have been reprogrammed to an opposite logic state, detecting third threshold voltages exhibited by the plurality of memory cells in response to application of the third read voltage, and based on the third threshold voltages, associating one of the first or second logic state to one or more of the cells of the of the plurality of memory cells. A related circuit, a related memory device and a related system are also disclosed.

公开(公告)号：US20210217470A1

公开(公告)日：2021-07-15

申请号：US16771177

申请日：2019-12-03

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C13/00

Abstract: The present disclosure provides a method, a circuit, and a system for reading memory cells. The method comprises: applying a first voltage with a first polarity to a plurality of the memory cells; applying a second voltage with a second polarity to one or more of said plurality of the memory cells; applying at least a third voltage with the first polarity to one or more of said plurality of the memory cells; detecting electrical responses of memory cells to the first voltage, the second voltage, and the third voltage; and determining a logic state of respective memory cells based on the electrical responses of the memory cells to the first voltage, the second voltage, and the third voltage.