公开(公告)号：US20200075087A1

公开(公告)日：2020-03-05

申请号：US16121448

申请日：2018-09-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vijayakrishna J. Vankayala

IPC: G11C11/406 ,  G06F1/10 ,  G06F3/06

Abstract: Devices and methods include organizing memory units of a memory device into a number of groups. The devices and methods also include self-refreshing each group of memory units on different corresponding sequential clock pulses of a self-refresh clock.

公开(公告)号：US20200075067A1

公开(公告)日：2020-03-05

申请号：US16121325

申请日：2018-09-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christian N. Mohr ,  Jennifer E. Taylor ,  Vijayakrishna J. Vankayala

IPC: G11C7/10

Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.

公开(公告)号：US10083723B1

公开(公告)日：2018-09-25

申请号：US15985118

申请日：2018-05-21

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala

IPC: G11C5/06 ,  H01L25/065 ,  G11C8/10

Abstract: Apparatuses and methods for transmitting die state information between a plurality of dies are described. An example apparatus includes: a plurality of dies, wherein each die of the plurality of dies includes a first through electrode and a second through electrode; a first path including the first electrodes of the plurality of dies in series; and a second path including the first electrodes of the plurality of dies in series. The first path transmits first internal state information related to a first state of at least one die of the plurality of dies. The second path transmits second internal state information related to a second state of at least one die of the plurality of dies.

公开(公告)号：US11955981B2

公开(公告)日：2024-04-09

申请号：US17723692

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala

IPC: H03L7/191 ,  G11C7/10 ,  H03K19/20 ,  H03L7/197

CPC classification number: H03L7/191 ,  G11C7/1039 ,  H03K19/20 ,  H03L7/1976

Abstract: A memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The memory device further includes multiple die stacked in a three-dimensional stack. A first die of the plurality of die includes a first plurality of memory cells and first local control circuitry. The first local circuitry includes division circuitry configured to receive the clock from the clock input, generate a divided clock having a lower frequency than that of the clock, and generate multiple clocks from the divided clock with each of the multiple clocks having a lower frequency than the divided clock. The memory device also includes one or more transmitters configured to transmit the multiple clocks using a inter-die interconnects between the multiple die.

公开(公告)号：US11887687B2

公开(公告)日：2024-01-30

申请号：US17652233

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/109 ,  G11C7/1012 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/1093

Abstract: Methods, systems, and devices for read operations for a memory array and register are described. In some examples, a memory device may include one or more memory arrays and one or more registers (e.g., one or more mode registers). The memory device may include circuitry that allows for a command to access a memory array and a command to access a register to be received consecutively (e.g., during consecutive sets of clock cycles). Because the commands may be received during consecutive sets of clock cycles, the corresponding data may also be output from the memory array and register during consecutive clock cycles.

公开(公告)号：US20230336181A1

公开(公告)日：2023-10-19

申请号：US17723692

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala

IPC: H03L7/191 ,  H03L7/197 ,  H03K19/20 ,  G11C7/10

CPC classification number: H03L7/191 ,  H03L7/1976 ,  H03K19/20 ,  G11C7/1039

Abstract: A memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The memory device further includes multiple die stacked in a three-dimensional stack. A first die of the plurality of die includes a first plurality of memory cells and first local control circuitry. The first local circuitry includes division circuitry configured to receive the clock from the clock input, generate a divided clock having a lower frequency than that of the clock, and generate multiple clocks from the divided clock with each of the multiple clocks having a lower frequency than the divided clock. The memory device also includes one or more transmitters configured to transmit the multiple clocks using a inter-die interconnects between the multiple die.

公开(公告)号：US11762786B2

公开(公告)日：2023-09-19

申请号：US17410623

申请日：2021-08-24

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala

IPC: G06F13/16 ,  G06F1/06 ,  G11C19/00

CPC classification number: G06F13/1668 ,  G06F1/06 ,  G11C19/00

Abstract: A memory device including memory cells operating according to a first clock signal having a first clock frequency and accessed based on a data access time. The memory device may include a clock shifter circuit for delaying the access commands based on the data access time. The clock shifter circuitry include a shift register circuit and a phase correction circuit. The shift register circuit delays the access commands using a second clock signal having a fraction of the first clock frequency. The phase correction circuit receives the access commands from the shift register circuitry using the fraction of the first clock frequency, delays the access commands based on phase information of the access commands, and outputs the access commands to the memory cells based on the data access time using the first clock frequency.

公开(公告)号：US11705429B2

公开(公告)日：2023-07-18

申请号：US17013225

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Jason M. Brown ,  Vijayakrishna J. Vankayala

IPC: G11C11/00 ,  H01L25/065 ,  G11C13/00 ,  G11C29/00 ,  H10B63/00

CPC classification number: H01L25/0657 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/702 ,  G11C13/003 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2013/0045 ,  H01L2225/06544 ,  H10B63/84

Abstract: A device may include a first die having a first circuit and a second die having a second circuit. The die may be separated by a material layer. The material layer may include multiple through-silicon vias (TSVs) for electrically coupling the first die to the second die. A first TSV of the TSVs may electrically couple the first circuit to the second circuit and a second TSV of the TSVs may include a redundant TSV that electrically bypasses the first TSV to couple the first circuit to the second circuit if a fault is detected in the first TSV.

公开(公告)号：US20230068313A1

公开(公告)日：2023-03-02

申请号：US17410623

申请日：2021-08-24

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala

IPC: G06F13/16 ,  G06F1/06

Abstract: A memory device including memory cells operating according to a first clock signal having a first clock frequency and accessed based on a data access time. The memory device may include a clock shifter circuit for delaying the access commands based on the data access time. The clock shifter circuitry include a shift register circuit and a phase correction circuit. The shift register circuit delays the access commands using a second clock signal having a fraction of the first clock frequency. The phase correction circuit receives the access commands from the shift register circuitry using the fraction of the first clock frequency, delays the access commands based on phase information of the access commands, and outputs the access commands to the memory cells based on the data access time using the first clock frequency.

公开(公告)号：US20220328098A1

公开(公告)日：2022-10-13

申请号：US17853563

申请日：2022-06-29

Applicant: Micron Technology, Inc.

Inventor： Jason M. Brown ,  Vijayakrishna J. Vankayala

IPC: G11C13/00 ,  H03L7/081

Abstract: Memory devices may have a memory array and a delay locked loop (DLL) circuit that adjusts signals associated with operations to access of the memory array. The memory device may also include a controller that delays an access command to access the memory array by transmitting the access command through delay circuitry of the DLL circuit. This may cause the access command to be delayed by a first duration of time when output from the delay circuitry. Delay of the access command may align a data signal and the access command such that the access command and a system clock may cause latching of suitable data of the data signal.