-
31.发明授权公开(公告)号：US11676650B2
公开(公告)日：2023-06-13
申请号：US17362822
申请日：2021-06-29
Applicant: Micron Technology, Inc.
Inventor： Kazutaka Miyano , Yasuo Satoh , Kenji Mae
IPC: G11C7/00 , G11C11/406 , H03L7/081
CPC classification number: G11C11/40615 , H03L7/0812
Abstract: A semiconductor device may include a delay locked loop (DLL) control circuit coupled to an update trigger generator and a DLL update circuit. The DLL control circuit may receive an update trigger signal and an internal refresh signal and configured to activate the DLL update circuit responsive to an update trigger in the update trigger signal and deactivate the DLL update circuit responsive to an active internal refresh signal. The DLL update circuit may perform DLL update to one or more memory cell arrays when activated and not perform DLL update to the memory cell arrays when deactivated. The DLL control circuit may reactivate the DLL update circuit once the internal refresh signal becomes inactive. In other scenarios, once the DLL update circuit is deactivated, the DLL update circuit stays deactivated until the next update trigger in the update trigger signal.
-
公开(公告)号：US20210313974A1
公开(公告)日：2021-10-07
申请号：US17353485
申请日：2021-06-21
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yasuo Satoh
Abstract: Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example apparatus includes a shift register that includes a plurality of registers coupled in series to one another. The plurality of registers are grouped into a first group of registers and a second group of registers. The first group of registers includes first and second registers. The second group of registers includes a third register. The first and second registers of the first group of registers are configured to receive in common an output of the third register of the second group of registers so that both the first and second registers store the output of the third register responsive to a shift clock.
-
公开(公告)号：US11115007B2
公开(公告)日：2021-09-07
申请号：US16294640
申请日：2019-03-06
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tyler J. Gomm , Yasuo Satoh
IPC: H03K3/037 , H03K3/017 , H03K19/20 , G11C11/4074 , G11C11/408 , G11C11/4076 , G11C7/10 , G11C11/4093 , G11C7/22
Abstract: Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an output signal. The two-phase flip-flop circuit includes a two-phase flip-flop and a driver circuit. The two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal. The first driver control signal and the second driver control signal are complementary. The driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal.
-
公开(公告)号：US11012060B2
公开(公告)日：2021-05-18
申请号：US16784002
申请日：2020-02-06
Applicant: Micron Technology, Inc.
Inventor： Yasuo Satoh
Abstract: Several embodiments of electrical circuit devices and systems with a duty cycle correction apparatus that includes a duty cycle adjustment circuit that is configured to adjust a duty cycle of the input clock signal based on an averaged code value. The duty cycle correction apparatus includes a duty cycle detector circuit that receives first and second clock signals from a clock distribution network. The duty cycle detector is configured to output a duty cycle status signal that indicates whether the first clock signal is above or below a 50% duty cycle based on a comparison of the first clock signal to the second clock signal. The duty cycle correction apparatus also includes a counter logic circuit configured to determine the average code value, and the counter logic circuit automatically cancels an offset of the duty cycle detector when determining the averaged code value.
-
公开(公告)号：US10931270B2
公开(公告)日：2021-02-23
申请号：US16725102
申请日：2019-12-23
Applicant: Micron Technology, Inc.
Inventor： Yasuo Satoh , Kazutaka Miyano
Abstract: Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.
-
Patent Agency Ranking
公开(公告)号：US10891989B2
公开(公告)日：2021-01-12
申请号：US16700250
申请日：2019-12-02
Applicant: Micron Technology, Inc.
Inventor： Yasuo Satoh , Yuan He
Abstract: A memory system includes an external calibration device that has a predetermined impedance and a first memory device with a first pad for selective connection to the external calibration device. The first memory device also includes an internal calibration device having an impedance that is programmable and a second pad connected to the internal calibration device. The system further includes a second memory device having a third pad for selective connection to the second pad of the first memory device. A processing device is operatively coupled to the first memory device and the second memory device. The processing device programs the impedance of the internal calibration device of the first memory device based on the external calibration device, and programs an impedance of a termination component in the second memory device based on the impedance of the internal calibration device of the first memory device.
-
公开(公告)号：US20200176036A1
公开(公告)日：2020-06-04
申请号：US16700250
申请日：2019-12-02
Applicant: Micron Technology, Inc.
Inventor： Yasuo Satoh , Yuan He
Abstract: A memory system includes an external calibration device that has a predetermined impedance and a first memory device with a first pad for selective connection to the external calibration device. The first memory device also includes an internal calibration device having an impedance that is programmable and a second pad connected to the internal calibration device. The system further includes a second memory device having a third pad for selective connection to the second pad of the first memory device. A processing device is operatively coupled to the first memory device and the second memory device. The processing device programs the impedance of the internal calibration device of the first memory device based on the external calibration device, and programs an impedance of a termination component in the second memory device based on the impedance of the internal calibration device of the first memory device.
-
公开(公告)号：US10270431B2
公开(公告)日：2019-04-23
申请号：US15717610
申请日：2017-09-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tyler J. Gomm , Yasuo Satoh
IPC: H03K19/20 , H03K3/037 , G11C11/4074 , G11C11/408
Abstract: Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an output signal. The two-phase flip-flop circuit includes a two-phase flip-flop and a driver circuit. The two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal. The first driver control signal and the second driver control signal are complementary. The driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal.
-
公开(公告)号：US10141942B1
公开(公告)日：2018-11-27
申请号：US15851126
申请日：2017-12-21
Applicant: Micron Technology, Inc.
Inventor： Yasuo Satoh
IPC: H03L7/06 , H03L7/08 , H03L7/089 , H03L7/197 , H03B19/00 , H03L7/14 , H04L7/04 , H03L7/087 , H04L5/26 , H03L7/18
Abstract: Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.
-
公开(公告)号：US20150109036A1
公开(公告)日：2015-04-23
申请号：US14058092
申请日：2013-10-18
Applicant: Micron Technology, Inc.
Inventor： Tyler J. Gomm , Yasuo Satoh
CPC classification number: H03K3/017 , H03K5/1565 , H03L7/06
Abstract: Methods and apparatuses are disclosed for preserving duty cycle at voltage domain boundaries. One example apparatus includes a complement generation circuit configured to generate a complementary signal responsive to an input signal. The complement generation circuit is configured to operate in a first voltage domain. The apparatus also includes a compensation circuit configured to generate a compensated signal by compensating the input signal for a delay corresponding to the complement generation circuit. The compensation circuit is configured to operate in a second voltage domain. The apparatus also includes a phase mixing circuit configured to combine the complementary signal and the compensated signal to generate an output signal.
Abstract translation: 公开了用于在电压域边界处保持占空比的方法和装置。 一个示例性装置包括补码生成电路，其被配置为响应于输入信号产生互补信号。 补码生成电路被配置为在第一电压域中操作。 该装置还包括补偿电路，其被配置为通过对与补码生成电路相对应的延迟补偿输入信号来产生补偿信号。 补偿电路被配置为在第二电压域中操作。 该装置还包括相位混合电路，该相位混合电路被配置为组合互补信号和经补偿的信号以产生输出信号。
-
-
-
-
-
-
-
-
-
Search Results
62
records
(took 0.023 seconds)
