公开(公告)号：US20080266969A1

公开(公告)日：2008-10-30

申请号：US12169142

申请日：2008-07-08

申请人： Ming-Chang Kuo ,  Chao-I Wu

发明人： Ming-Chang Kuo ,  Chao-I Wu

IPC分类号： G11C16/06 ,  H01L29/792

CPC分类号： G11C16/0475 ,  G11C16/12

摘要： A method of operating a non-volatile memory having a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer close to the drain region is a data storage region. Before prosecuting the operation, electrons have been injected into the auxiliary charge region. When prosecuting the programming operation, a first voltage is applied to the gate, a second voltage is applied to the source region, a third voltage is applied to the drain region and a fourth voltage is applied to the substrate. The first voltage is greater than the fourth voltage, the third voltage is greater than the second voltage, and the second voltage is greater than the fourth voltage to initiate a channel initiated secondary hot electron injection to inject electrons into the data storage region.

摘要翻译： 提供一种操作具有基板，栅极，电荷俘获层，源极区域和漏极区域的非易失性存储器的方法。 靠近源区的电荷捕获层是辅助电荷区，靠近漏极区的电荷捕获层是数据存储区。 在起诉前，电子注入到辅助电荷区域。 当起动编程操作时，向栅极施加第一电压，将第二电压施加到源极区域，向漏极区域施加第三电压，并向衬底施加第四电压。 第一电压大于第四电压，第三电压大于第二电压，第二电压大于第四电压，以启动通道启动的次级热电子注入以将电子注入数据存储区域。

公开(公告)号：US20060146603A1

公开(公告)日：2006-07-06

申请号：US11292024

申请日：2005-12-01

申请人： Ming-Chang Kuo ,  Chao-I Wu ,  Ming-Hsin Lee ,  Tzu-Hsuan Hsu

发明人： Ming-Chang Kuo ,  Chao-I Wu ,  Ming-Hsin Lee ,  Tzu-Hsuan Hsu

IPC分类号： G11C11/34

CPC分类号： G11C16/0466 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/7887 ,  H01L29/7923

摘要： A method is provided of forming an assisted charge memory (AC-memory) cell. The method uses a two-sided charge trap memory cell that includes a two-sided charge trapping layer. A charge is formed in at least a portion of the two-sided charge trapping layer. One side (AC-side) of the two-sided charge trapping layer always has a fixed high threshold voltage (Vt) level which is the assisted charge for the AC-memory cell. The other side (data-side) is used for memory operations.

公开(公告)号：US20080316810A1

公开(公告)日：2008-12-25

申请号：US11767980

申请日：2007-06-25

申请人： Ming-Chang Kuo ,  Chao-I Wu

发明人： Ming-Chang Kuo ,  Chao-I Wu

IPC分类号： G11C11/00 ,  G11C16/04 ,  G11C7/10 ,  H01L29/788

CPC分类号： H01L29/42324 ,  G11C11/4125 ,  G11C14/00 ,  G11C14/0063

摘要： A memory unit is provided herein. Two non-volatile devices are used to store a logic state of the memory unit into the non-volatile devices. Although a power supply for the memory unit is shut down, the non-volatile devices still keep the data stored therein. The present invention not only has an advantage of high speed operation of a static random access memory (SRAM), but also has a function for storing data of a non-volatile memory.

摘要翻译： 本文提供了存储单元。 两个非易失性设备用于将存储器单元的逻辑状态存储到非易失性设备中。 虽然存储器单元的电源被关闭，但是非易失性设备仍然保持存储在其中的数据。 本发明不仅具有静态随机存取存储器（SRAM）的高速操作的优点，而且具有用于存储非易失性存储器的数据的功能。

公开(公告)号：US08304755B2

公开(公告)日：2012-11-06

申请号：US12372860

申请日：2009-02-18

申请人： Ming-Chang Kuo

发明人： Ming-Chang Kuo

IPC分类号： H01L47/00

CPC分类号： G11C11/5685 ,  G11C13/0007 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

摘要： A three-dimensional (3D) semiconductor structure with high density and method of fabricating the same are disclosed. The 3D semiconductor structure comprises at least a first memory cell and a second memory cell stacked on the first memory cell. The first memory cell comprises a first conductive line and a second conductive line. The second memory cell comprises another first conductive line opposite to the first conductive line of the first memory cell, and the second conductive line formed between said two first conductive lines of the first and second memory cells. The first and second memory cells share the second conductive line when the 3D semiconductor structure is programming and erasing, and each of the first and second memory cells has a diode.

摘要翻译： 公开了一种具有高密度的三维（3D）半导体结构及其制造方法。 3D半导体结构包括至少第一存储单元和堆叠在第一存储单元上的第二存储单元。 第一存储单元包括第一导线和第二导线。 第二存储单元包括与第一存储单元的第一导线相对的另一第一导线，以及形成在第一和第二存储单元的所述两个第一导线之间的第二导线。 当3D半导体结构编程和擦除时，第一和第二存储单元共享第二导线，并且第一和第二存储单元中的每一个具有二极管。

公开(公告)号：US07936607B2

公开(公告)日：2011-05-03

申请号：US12465872

申请日：2009-05-14

申请人： Ming-Chang Kuo

发明人： Ming-Chang Kuo

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3404

摘要： A non-volatile memory includes a plurality of cells on a substrate of a first conductivity type, each cell including a portion of the substrate, a control gate, a charge-storing layer between the portion of the substrate and the control gate, and two S/D regions of a second conductivity type in the portion of the substrate. A circuit provides a first voltage to the substrate and a second voltage to both S/D regions of each cell, wherein the difference between the first and second voltages is sufficient to cause band-to-band tunneling hot holes. The circuit also provides a voltage to the control gate and the period of applying the voltages are controlled such that the threshold voltages of all the cells converge in a tolerable range.

摘要翻译： 非挥发性存储器包括在第一导电类型的衬底上的多个单元，每个单元包括衬底的一部分，控制栅极，在衬底的部分和控制栅极之间的电荷存储层，以及两个 第二导电类型的S / D区域在衬底的该部分中。 电路向基板提供第一电压，并向每个单元的两个S / D区域提供第二电压，其中第一和第二电压之间的差值足以引起带对隧道的热孔。 电路还向控制栅极提供电压，并且控制施加电压的周期使得所有单元的阈值电压在可容许的范围内收敛。

公开(公告)号：US20110013462A1

公开(公告)日：2011-01-20

申请号：US12889710

申请日：2010-09-24

申请人： Ming-Chang Kuo

发明人： Ming-Chang Kuo

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C11/5621 ,  G11C16/0416

摘要： A memory operating method includes the following steps. First, a memory with a charge storage structure is provided. Next, the memory is biased to a first threshold voltage. Then, the memory is biased to a second threshold voltage. Next, the memory is biased to a third threshold voltage. The first threshold voltage is higher than a first level. The second threshold voltage is lower than a second level. The third threshold voltage is approximating or equal to the second level.

摘要翻译： 存储器操作方法包括以下步骤。 首先，提供具有电荷存储结构的存储器。 接下来，存储器被偏置到第一阈值电压。 然后，存储器被偏置到第二阈值电压。 接下来，存储器被偏置到第三阈值电压。 第一阈值电压高于第一电平。 第二阈值电压低于第二电平。 第三阈值电压接近或等于第二电平。

公开(公告)号：US07778081B2

公开(公告)日：2010-08-17

申请号：US11945181

申请日：2007-11-26

申请人： Ming-Chang Kuo

发明人： Ming-Chang Kuo

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486

摘要： A method for performing operations on a memory cell is described. The memory cell includes a substrate, a first doping region and a second doping region. The first doping region and the second doping region are formed on the substrate with a channel region therebetween. A dielectric layer is formed above the channel region and a conductive gate is formed over the dielectric layer. The method includes applying a first constant voltage for a first period to the conductive gate followed by applying a second constant voltage for a second period to the conductive gate repeatedly. The value of the first constant voltage is different from the value of the second constant voltage. A third constant voltage and a fourth voltage are applied to the first doping region and the second doping region respectively.

摘要翻译： 描述了对存储器单元执行操作的方法。 存储单元包括衬底，第一掺杂区和第二掺杂区。 第一掺杂区域和第二掺杂区域形成在衬底上，其间具有沟道区域。 介电层形成在沟道区上方，导电栅极形成在电介质层的上方。 该方法包括将第一周期的第一恒定电压施加到导电栅极，然后将第二周期的第二恒定电压重复施加到导电栅极。 第一恒定电压的值与第二恒定电压的值不同。 第三恒定电压和第四电压分别施加到第一掺杂区域和第二掺杂区域。

公开(公告)号：US07655970B2

公开(公告)日：2010-02-02

申请号：US11359028

申请日：2006-02-22

申请人： Ming-Chang Kuo

发明人： Ming-Chang Kuo

IPC分类号： H01L29/94

CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825

摘要： A non-volatile memory device comprises a substrate with the dielectric layer formed thereon. A control gate and a floating gate are then formed next to each other on top of the dielectric layer separated by a gap. Accordingly, a non-volatile memory device can be constructed using a single poly process that is compatible with conventional CMOS processes. In addition, assist gates are formed on the dielectric layer next to the control gate and floating gate respectively.

摘要翻译： 非易失性存储器件包括其上形成有电介质层的衬底。 然后在由间隙分开的电介质层的顶部上彼此相邻地形成控制栅极和浮置栅极。 因此，可以使用与常规CMOS工艺兼容的单一多工艺来构造非易失性存储器件。 另外，分别在控制栅极和浮动栅极旁边的电介质层上形成辅助栅极。

公开(公告)号：US20090185428A1

公开(公告)日：2009-07-23

申请号：US12017573

申请日：2008-01-22

申请人： Ming-Chang Kuo

发明人： Ming-Chang Kuo

IPC分类号： G11C16/34 ,  G11C16/06

CPC分类号： G11C16/3468 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0466 ,  G11C2211/5621 ,  G11C2211/5648

摘要： An operating method of a memory cell is described, wherein the memory cell has a plurality of threshold voltages. The operating method includes programming the cell from an initial state to a programmed state. The initial state is an erased state having a threshold voltage between the lowest threshold voltage and the highest one among the plurality of threshold voltages.

摘要翻译： 描述存储单元的操作方法，其中存储单元具有多个阈值电压。 操作方法包括将单元从初始状态编程到编程状态。 初始状态是具有阈值电压在多个阈值电压中的最低阈值电压和最高阈值电压之间的擦除状态。

公开(公告)号：US07554851B2

公开(公告)日：2009-06-30

申请号：US11620450

申请日：2007-01-05

申请人： Ming-Chang Kuo

发明人： Ming-Chang Kuo

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3404

摘要： A reset method of a non-volatile memory is described. The non-volatile memory includes a plurality of cells on a substrate of a first conductivity type, each including a portion of the substrate, a control gate, a charge-storing layer between the portion of the substrate and the control gate, and two S/D regions of a second conductivity type in the portion of the substrate. The reset method utilizes a DSB-BTBTHH effect. A first voltage is applied to the substrate and a second voltage to both S/D regions of each cell, wherein the difference between the first and second voltages is sufficient to cause band-to-band tunneling hot holes. A voltage applied to the control gate and the period of applying the voltages are controlled such that the threshold voltages of all the cells converge in a tolerable range.

摘要翻译： 描述非易失性存储器的复位方法。 非易失性存储器包括在第一导电类型的衬底上的多个单元，每个单元包括衬底的一部分，控制栅极，在衬底的部分和控制栅极之间的电荷存储层，以及两个S / D区域的第二导电类型。 复位方法使用DSB-BTBTHH效果。 向基板施加第一电压，对每个单元的两个S / D区域施加第二电压，其中第一和第二电压之间的差异足以引起带对隧道的热孔。 控制施加到控制栅极的电压和施加电压的周期，使得所有单元的阈值电压在可容许的范围内收敛。