公开(公告)号：US20120013402A1

公开(公告)日：2012-01-19

申请号：US12804318

申请日：2010-07-19

申请人： Jungwoo Song ,  Xicheng Jiang ,  Minsheng Wang ,  Todd L. Brooks

发明人： Jungwoo Song ,  Xicheng Jiang ,  Minsheng Wang ,  Todd L. Brooks

IPC分类号： H03F1/00

CPC分类号： H03F3/217

摘要： Disclosed is a closed-loop class-D amplifier circuit including a modulated reference signal generator that provides a modulated reference signal in a feed-forward path, where the reference signal is modulated corresponding to an input signal. The closed-loop class-D amplifier circuit further includes a comparator to generate a control signal based on a comparison of the modulated reference signal and a correction signal, which in turn is produced by filtering a combination of the input signal and a feedback signal. The closed-loop class-D amplifier circuit also includes a pulse generator to generate a pulse-width-modulated signal to drive an output stage of the closed-loop class-D amplifier based on the control signal.

摘要翻译： 公开了一种闭环D类放大器电路，其包括在前馈路径中提供调制参考信号的调制参考信号发生器，其中参考信号根据输入信号被调制。 闭环D类放大器电路还包括比较器，用于基于调制参考信号和校正信号的比较产生控制信号，校正信号又通过滤波输入信号和反馈信号的组合来产生。 闭环D类放大器电路还包括脉冲发生器，以产生脉冲宽度调制信号，以根据控制信号驱动闭环D类放大器的输出级。

公开(公告)号：US08060050B2

公开(公告)日：2011-11-15

申请号：US10926763

申请日：2004-08-26

申请人： Yue Chen ,  Nelson Sollenberger ,  Minsheng Wang

发明人： Yue Chen ,  Nelson Sollenberger ,  Minsheng Wang

IPC分类号： H04B1/16

CPC分类号： H04L27/38

摘要： In a wireless device, a method and system for a baseband receiver interface including analog and digital components are provided. An analog or a digital interface may be selected for a I/Q data signal received from a front-end receiver. The analog interface may be a conventional RF or a VLIF interface. The I/Q data signal may be digitized when received from the analog interface and saturation detection may be used during digitization of the I/Q data signal. When the analog interface is the VLIF interface, a derotator may be used to remove the VLIF frequency. The derotator may be based on a CORDIC algorithm. The I/Q data signal may be converted from serial to parallel format when received from the digital interface. The received I/Q data signal may be decimated before transferred to a baseband processor.

摘要翻译： 在无线设备中，提供了包括模拟和数字组件的用于基带接收器接口的方法和系统。 可以为从前端接收机接收的I / Q数据信号选择模拟或数字接口。 模拟接口可以是传统的RF或VLIF接口。 当从模拟接口接收时，I / Q数据信号可以被数字化，并且在数字化I / Q数据信号期间可以使用饱和检测。 当模拟接口是VLIF接口时，可以使用解旋器去除VLIF频率。 解旋器可以基于CORDIC算法。 当从数字接口接收时，I / Q数据信号可以从串行转换为并行格式。 接收的I / Q数据信号可以在传送到基带处理器之前被抽取。

公开(公告)号：US07714675B2

公开(公告)日：2010-05-11

申请号：US11566995

申请日：2006-12-05

申请人： Minsheng Wang

发明人： Minsheng Wang

IPC分类号： H03K7/08 ,  H03M3/00

CPC分类号： H03F3/217

摘要： Methods and systems for modulating an input electrical signal are disclosed and may comprise modulating input signals utilizing a digital Class-D modulator and generating a digital output signal that is proportional to the input signals. The digital Class-D modulator may be comprised of four stages. To avoid integrator saturation, the output of at least one integrator stage may be limited by utilizing limiters in integrator feedback loops. The digital Class-D modulator utilizes a pulse width modulation technique. For increased signal to noise ratio (SNR) at a desired output power, the magnitude of a triangular waveform oscillator voltage may be greater than the magnitude of an integrated input signal. The digital output signal may be fed back to an input of at least one of the four stages in the digital Class-D modulator. The triangular waveform oscillator frequency may be adjusted to match desired output frequency.

摘要翻译： 公开了用于调制输入电信号的方法和系统，并且可以包括利用数字D类调制器来调制输入信号并产生与输入信号成比例的数字输出信号。 数字D类调制器可以由四个阶段组成。 为了避免积分器饱和，可以通过利用积分器反馈回路中的限制器来限制至少一个积分器级的输出。 数字D类调制器采用脉宽调制技术。 为了在期望的输出功率下提高信噪比（SNR），三角波形振荡器电压的幅度可能大于积分输入信号的幅度。 数字输出信号可以被反馈到数字D类调制器中的四个级中的至少一个的输入。 可以调整三角波形振荡器频率以匹配所需的输出频率。

公开(公告)号：US07123177B2

公开(公告)日：2006-10-17

申请号：US10640633

申请日：2003-08-14

申请人： Taiyi Cheng ,  Josephus van Engelen ,  Minsheng Wang

发明人： Taiyi Cheng ,  Josephus van Engelen ,  Minsheng Wang

IPC分类号： H03M3/00

CPC分类号： H03M3/444 ,  H03M3/43

摘要： A system and method is provided for stabilizing high order sigma delta modulators. The system includes an integrator having a limiter in the feedback path of the integrator. The integrator combines an input signal with a feedback signal generated by the limiter to produce an integrated output signal. The output signal is output to the next component of the sigma delta modulator. In addition, the output signal is fed back through the limiter. When an output signal received in the feedback path by the limiter exceeds the threshold value of the limiter, the limiter is activated and clamps the output signal to produce a limited signal. The limited signal is combined with the input signal to the integrator to produce the output signal.

摘要翻译： 提供了一种用于稳定高阶Σ-Δ调制器的系统和方法。 该系统包括在积分器的反馈路径中具有限幅器的积分器。 积分器将输入信号与限幅器产生的反馈信号相结合，产生一个集成的输出信号。 输出信号输出到Σ-Δ调制器的下一个分量。 此外，输出信号通过限幅器反馈。 当限制器在反馈路径中接收的输出信号超过限幅器的阈值时，限幅器被激活并钳位输出信号以产生有限的信号。 有限信号与输入信号组合到积分器以产生输出信号。

公开(公告)号：US20060087463A1

公开(公告)日：2006-04-27

申请号：US11250374

申请日：2005-10-17

申请人： Minsheng Wang

发明人： Minsheng Wang

IPC分类号： H03M1/10

CPC分类号： H03M3/358 ,  H03M3/436

摘要： An error feedback circuit includes a first summer receiving an analog input signal and a feedback signal and outputting a summed signal. A quantizer receives the summed signal and outputs a quantized output signal. A limiter receives the summed signal and outputs a limited summed signal. The limiter limits the limited summed signal to α* (maximum value of input signal), α>1. A second summer receives the limited summed signal and the output signal and outputs an error signal. A filter receives the error signal and outputting the feedback signal. Typically, 1.0

摘要翻译： 误差反馈电路包括接收模拟输入信号和反馈信号的第一加法器，并输出求和信号。 量化器接收加法信号并输出​​量化的输出信号。 限幅器接收相加的信号并输出​​有限的求和信号。 限制器将有限的求和信号限制为alpha *（输入信号的最大值），alpha> 1。 第二个夏天接收有限的求和信号和输出信号并输出​​一个误差信号。 滤波器接收误差信号并输出​​反馈信号。 通常，1.0 <2.0，更优选1.4 <α1.6。 滤波器具有H 1（z）= 2z-1的传递函数-z-2S 。

公开(公告)号：US20050272400A1

公开(公告)日：2005-12-08

申请号：US10926763

申请日：2004-08-26

申请人： Yue Chen ,  Minsheng Wang

发明人： Yue Chen ,  Minsheng Wang

IPC分类号： H04L25/02 ,  H04L27/38 ,  H03M1/00 ,  H01Q11/12 ,  H04B1/04

CPC分类号： H04L27/38

摘要： In a wireless device, a method and system for a baseband receiver interface including analog and digital components are provided. An analog or a digital interface may be selected for a I/Q data signal received from a front-end receiver. The analog interface may be a conventional RF or a VLIF interface. The I/Q data signal may be digitized when received from the analog interface and saturation detection may be used during digitization of the I/Q data signal. When the analog interface is the VLIF interface, a derotator may be used to remove the VLIF frequency. The derotator may be based on a CORDIC algorithm. The I/Q data signal may be converted from serial to parallel format when received from the digital interface. The received I/Q data signal may be decimated before transferred to a baseband processor.

摘要翻译： 在无线设备中，提供了包括模拟和数字组件的用于基带接收器接口的方法和系统。 可以为从前端接收机接收的I / Q数据信号选择模拟或数字接口。 模拟接口可以是传统的RF或VLIF接口。 当从模拟接口接收时，I / Q数据信号可以被数字化，并且在数字化I / Q数据信号期间可以使用饱和检测。 当模拟接口是VLIF接口时，可以使用解旋器去除VLIF频率。 解旋器可以基于CORDIC算法。 当从数字接口接收时，I / Q数据信号可以从串行转换为并行格式。 接收的I / Q数据信号可以在传送到基带处理器之前被抽取。

公开(公告)号：US06956513B1

公开(公告)日：2005-10-18

申请号：US10969852

申请日：2004-10-22

申请人： Minsheng Wang

发明人： Minsheng Wang

IPC分类号： H03M3/00

CPC分类号： H03M3/358 ,  H03M3/436

摘要： An error feedback circuit includes a first summer receiving an analog input signal and a feedback signal and outputting a summed signal. A quantizer receives the summed signal and outputs a quantized output signal. A limiter receives the summed signal and outputs a limited summed signal. The limiter limits the limited summed signal to α*(maximum value of input signal), α>1. A second summer receives the limited summed signal and the output signal and outputs an error signal. A filter receives the error signal and outputting the feedback signal. Typically, 1.0

摘要翻译： 误差反馈电路包括接收模拟输入信号和反馈信号的第一加法器，并输出求和信号。 量化器接收加法信号并输出​​量化的输出信号。 限幅器接收相加的信号并输出​​有限的求和信号。 限制器将有限的求和信号限制为alpha *（输入信号的最大值），alpha> 1。 第二个夏天接收有限的求和信号和输出信号并输出​​一个误差信号。 滤波器接收误差信号并输出​​反馈信号。 通常，1.0 <2.0，更优选1.4 <α1.6。 滤波器具有H 1（z）= 2z-1的传递函数-z-2S 。

公开(公告)号：US06925171B2

公开(公告)日：2005-08-02

申请号：US10159524

申请日：2002-05-30

申请人： Minsheng Wang ,  Richard K. Hester

发明人： Minsheng Wang ,  Richard K. Hester

IPC分类号： H04J3/16 ,  H04M1/00 ,  H04M3/00

CPC分类号： H04M3/005

摘要： A codifier/decodifier (CODEC) filter circuit (250) connected in a subscriber line interface circuit (202) includes a transmit section (264, 262, 260) for converting differential voltage audio transmit signals representing voice transmissions from the subscriber instrument (202) into encoded digital data for transmission to the digital switching network. A receive section (254, 252) coupled between the digital switching network and subscriber instrument (202) within CODEC (250) for converting encoded digital data representing voice signals switched through the digital switching network to differential voltage audio receive signals for transmission to the subscriber instrument (202). The subscriber loop and subscriber instrument (202) reflect the digital voltage audio signals to the transmit section (264, 262, 260). An impedance section (258, 256) within CODEC (250) connects between the transmit section (264, 262, 260) and the receive section (254, 252) and is disposed to provide an audio band feedback signal between the transmit section (264, 262, 260) and the receive section (254, 252) for synthesizing a source impedance for the subscriber line that matches the subscriber loop impedance. Impedance section (258, 256) includes an analog impedance scaling network (246) coupled between the transmit section (264, 262, 260) and receive section (254, 252). The impedance section (258, 256) also includes a programmable digital filter (258) coupled to the transmit section (264, 262, 260) having a transfer function equal to: (R2T)(1+z−1)/(R1(T+2C2R2)(1+(T−2R2C2)/(T+2R2C2)z−1) where R2 is the second subscriber loop impedance, C2 is the subscriber loop capacitance, R1 is the first subscriber loop impedance, T is the sampling rate of the analog-to-digital converter and z is the frequency of the signal. Furthermore, a summer circuit (256) provides feedback between the programmable digital filter (258) and the receive section (254, 252) by summing the single-ended audio receive signals from the digital switching network with the audio band feedback signal output by the programmable digital filter (258).

公开(公告)号：US06856267B1

公开(公告)日：2005-02-15

申请号：US10778193

申请日：2004-02-17

申请人： Minsheng Wang ,  Jungwoo Song

发明人： Minsheng Wang ,  Jungwoo Song

IPC分类号： H03M3/00 ,  H03M7/32

CPC分类号： H03M7/3042

摘要： Provided are a system and method for implementing a multirate analog finite impulse response (FIR) filter. A system of the present invention includes a modulator having a first adder and a quantizer. The first adder includes an output port, and the quantizer includes (i) an input port coupled to the first adder output port and (ii) a quantizer output port. A second adder is also included, having one input port coupled to the first adder output port and another input port coupled to the quantizer output port. Also included are at least two two-unit delays, a first of the two-unit delays having an input port coupled to an output port of the second adder, and an output port coupled to an input port of the second of the two-unit delays. An output port of the second two-unit delays is coupled to a first input port of the first adder.

公开(公告)号：US06842130B2

公开(公告)日：2005-01-11

申请号：US10812975

申请日：2004-03-31

申请人： Minsheng Wang ,  Anil Tammineedi

发明人： Minsheng Wang ,  Anil Tammineedi

IPC分类号： G06F7/76 ,  H03M1/06 ,  H03M3/04 ,  H03M3/00

CPC分类号： G06F7/762 ,  H03M1/0665 ,  H03M3/338 ,  H03M3/464 ,  H03M3/502

摘要： A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0′, x1′} such that a number of 1's at bit x0′ over time is within ∀1 of a number of 1's at bit x1′. At least two 4-bit vector shufflers input the vectors {x0′, x1′}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0′, x1′} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0′, x1′} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.

摘要翻译： 用于混洗输入比特的数据洗牌装置包括多个比特洗牌器，每个比特混洗器输入相应的输入比特的两个比特x0和x1，并输出一个向量{x0'，x1'}，使得随着时间的推移，比特x0' 在位x1'的1的1'内。 至少两个4位向量混洗器输入向量{x0'，x1'}和输出4位向量，每个4位向量对应于由位产生的对应的两个向量{x0'，x1'}的组合 使得4位向量混洗器以与位混合器对位x0和x1进行操作相同的方式对矢量{x0'，x1'}进行操作。 基于4位向量洗牌器的下一个状态来更新位洗牌器的当前状态。