Method and system for codec with polyringer
    1.
    发明申请
    Method and system for codec with polyringer 有权
    多音节编解码器的方法和系统

    公开(公告)号:US20050278044A1

    公开(公告)日:2005-12-15

    申请号:US10926762

    申请日:2004-08-26

    IPC分类号: G06F17/00 G10H7/00

    摘要: In an audio processing device, a method and system for improved CODEC with polyringer are provided. An audio CODEC may comprise an audio ADC, an audio DAC, and a sidetone generator. Data from an external microphone may be processed by an audio ADC and may be sent to a processor that may be adapted to perform digital signal processing operations. The audio DAC may receive from the processor digital audio and polyphonic ringer data and may process the digital audio and polyphonic ringer data through separate digital filters and digital interpolators. The audio DAC may add the processed digital audio and polyphonic ringer data before analog conversion. The audio DAC may perform analog conversion by utilizing a delta-sigma demodulator, a current-based DAC, and a switched-capacitor filter. The converted data may be filtered with an RC filter and may be utilized to drive an external speaker or earpiece.

    摘要翻译: 在一种音频处理装置中,提供了一种用于改进具有多声道的CODER的方法和系统。 音频CODEC可以包括音频ADC,音频DAC和侧音发生器。 来自外部麦克风的数据可以由音频ADC处理,并且可以被发送到可适于执行数字信号处理操作的处理器。 音频DAC可以从处理器接收数字音频和复音振铃器数据,并且可以通过单独的数字滤波器和数字内插器处理数字音频和复音振铃器数据。 音频DAC可以在模拟转换之前添加经处理的数字音频和复音振铃器数据。 音频DAC可以通过利用Δ-Σ解调器,基于电流的DAC和开关电容滤波器来执行模拟转换。 转换的数据可以用RC滤波器滤波,并且可以用于驱动外部扬声器或听筒。

    Method and system for analog and digital RF receiver interface
    2.
    发明授权
    Method and system for analog and digital RF receiver interface 有权
    模拟和数字射频接收机接口的方法和系统

    公开(公告)号:US08060050B2

    公开(公告)日:2011-11-15

    申请号:US10926763

    申请日:2004-08-26

    IPC分类号: H04B1/16

    CPC分类号: H04L27/38

    摘要: In a wireless device, a method and system for a baseband receiver interface including analog and digital components are provided. An analog or a digital interface may be selected for a I/Q data signal received from a front-end receiver. The analog interface may be a conventional RF or a VLIF interface. The I/Q data signal may be digitized when received from the analog interface and saturation detection may be used during digitization of the I/Q data signal. When the analog interface is the VLIF interface, a derotator may be used to remove the VLIF frequency. The derotator may be based on a CORDIC algorithm. The I/Q data signal may be converted from serial to parallel format when received from the digital interface. The received I/Q data signal may be decimated before transferred to a baseband processor.

    摘要翻译: 在无线设备中,提供了包括模拟和数字组件的用于基带接收器接口的方法和系统。 可以为从前端接收机接收的I / Q数据信号选择模拟或数字接口。 模拟接口可以是传统的RF或VLIF接口。 当从模拟接口接收时,I / Q数据信号可以被数字化,并且在数字化I / Q数据信号期间可以使用饱和检测。 当模拟接口是VLIF接口时,可以使用解旋器去除VLIF频率。 解旋器可以基于CORDIC算法。 当从数字接口接收时,I / Q数据信号可以从串行转换为并行格式。 接收的I / Q数据信号可以在传送到基带处理器之前被抽取。

    Method and system for analog and digital RF receiver interface
    3.
    发明申请
    Method and system for analog and digital RF receiver interface 有权
    模拟和数字射频接收机接口的方法和系统

    公开(公告)号:US20050272400A1

    公开(公告)日:2005-12-08

    申请号:US10926763

    申请日:2004-08-26

    CPC分类号: H04L27/38

    摘要: In a wireless device, a method and system for a baseband receiver interface including analog and digital components are provided. An analog or a digital interface may be selected for a I/Q data signal received from a front-end receiver. The analog interface may be a conventional RF or a VLIF interface. The I/Q data signal may be digitized when received from the analog interface and saturation detection may be used during digitization of the I/Q data signal. When the analog interface is the VLIF interface, a derotator may be used to remove the VLIF frequency. The derotator may be based on a CORDIC algorithm. The I/Q data signal may be converted from serial to parallel format when received from the digital interface. The received I/Q data signal may be decimated before transferred to a baseband processor.

    摘要翻译: 在无线设备中,提供了包括模拟和数字组件的用于基带接收器接口的方法和系统。 可以为从前端接收机接收的I / Q数据信号选择模拟或数字接口。 模拟接口可以是传统的RF或VLIF接口。 当从模拟接口接收时,I / Q数据信号可以被数字化,并且在数字化I / Q数据信号期间可以使用饱和检测。 当模拟接口是VLIF接口时,可以使用解旋器去除VLIF频率。 解旋器可以基于CORDIC算法。 当从数字接口接收时,I / Q数据信号可以从串行转换为并行格式。 接收的I / Q数据信号可以在传送到基带处理器之前被抽取。

    Method and system for codec with polyringer
    4.
    发明授权
    Method and system for codec with polyringer 有权
    多音节编解码器的方法和系统

    公开(公告)号:US07653204B2

    公开(公告)日:2010-01-26

    申请号:US10926762

    申请日:2004-08-26

    IPC分类号: H04B1/00

    摘要: In an audio processing device, a method and system for improved CODEC with polyringer are provided. An audio CODEC may comprise an audio ADC, an audio DAC, and a sidetone generator. Data from an external microphone may be processed by an audio ADC and may be sent to a processor that may be adapted to perform digital signal processing operations. The audio DAC may receive from the processor digital audio and polyphonic ringer data and may process the digital audio and polyphonic ringer data through separate digital filters and digital interpolators. The audio DAC may add the processed digital audio and polyphonic ringer data before analog conversion. The audio DAC may perform analog conversion by utilizing a delta-sigma modulator, a current-based DAC, and a switched-capacitor filter. The converted data may be filtered with an RC filter and may be utilized to drive an external speaker or earpiece.

    摘要翻译: 在一种音频处理装置中,提供了一种用于改进具有多声道的CODER的方法和系统。 音频CODEC可以包括音频ADC,音频DAC和侧音发生器。 来自外部麦克风的数据可以由音频ADC处理,并且可以被发送到可适于执行数字信号处理操作的处理器。 音频DAC可以从处理器接收数字音频和复音振铃器数据,并且可以通过单独的数字滤波器和数字内插器处理数字音频和复音振铃器数据。 音频DAC可以在模拟转换之前添加经处理的数字音频和复音振铃器数据。 音频DAC可以通过利用Δ-Σ调制器,基于电流的DAC和开关电容滤波器来执行模拟转换。 转换的数据可以用RC滤波器滤波,并且可以用于驱动外部扬声器或听筒。

    Method of adding encoded range-of-interest location, type, and adjustable quantization parameters per macroblock to video stream

    公开(公告)号:US11533493B2

    公开(公告)日:2022-12-20

    申请号:US17158102

    申请日:2021-01-26

    IPC分类号: H04N19/176 H04N19/124

    摘要: A video encoding method is provided in the present invention. The method includes: determining a range of interest ROI in an ith frame, wherein the ROI comprises at least one ROI macroblock; extracting characteristic information of the at least one ROI macroblock, wherein the characteristic information comprises location information and type information of the at least one ROI macroblock; determining a quantization parameter QP corresponding to each of the at least one ROI macroblock; encoding the characteristic information of the at least one ROI macroblock according to the determined QP corresponding to each ROI macroblock, to obtain an ROI characteristic stream of the ith frame; and adding, to a video stream of the ith frame, the QP corresponding to each ROI macroblock and the ROI characteristic stream of the ith frame, to perform sending, wherein the video stream of the ith frame is obtained by encoding the ROI and a non-ROI comprised in the ith frame.

    Mobile terminal unlock method for security protection of mobile phone

    公开(公告)号:US10477004B1

    公开(公告)日:2019-11-12

    申请号:US16516478

    申请日:2019-07-19

    摘要: A mobile terminal unlock method for security protection of mobile phone is provided. The method includes: obtaining a trigger signal for unlock, and generating a first password according to the trigger signal; generating a corresponding unlock signal according to a preset correspondence between the unlock signal and the first password and with reference to the first password, and sending the corresponding unlock signal; obtaining an unlock password that is obtained by means of parsing by a user according to the unlock signal; matching the unlock password with the first password; determining whether the unlock password is consistent with the first password; and if a determining result is yes, unlocking a password lock; or if a determining result is no, obtaining a trigger signal for unlock again.

    Distortion limiter and automatic power control for drivers
    7.
    发明授权
    Distortion limiter and automatic power control for drivers 有权
    扭矩限制器和驱动程序的自动功率控制

    公开(公告)号:US09124227B2

    公开(公告)日:2015-09-01

    申请号:US13622170

    申请日:2012-09-18

    摘要: Systems and methods are disclosed to provide automatic power control for a driver circuit. Embodiments disclosed herein enable a driver circuit to automatically decrease the gain of amplified input signals when output power exceeds a threshold. Further, embodiments disclosed herein enable a driver circuit to automatically increase the gain of amplified input signals when battery supply voltage drops to avoid unwanted output signal distortion. By using reference signals for battery power and amplified signal input, the amplifiers of the driver circuit can be automatically adjusted until an equilibrium is reached.

    摘要翻译: 公开了系统和方法来为驱动器电路提供自动功率控制。 当输出功率超过阈值时,本文公开的实施例使得驱动器电路能够自动降低放大的输入信号的增益。 此外,本文公开的实施例使得当电池电源电压下降时,驱动器电路自动地增加放大的输入信号的增益,以避免不期望的输出信号失真。 通过使用电池电源和放大信号输入的参考信号,可以自动调节驱动电路的放大器,直到达到平衡。

    Distortion Limiter and Automatic Power Control for Drivers
    8.
    发明申请
    Distortion Limiter and Automatic Power Control for Drivers 有权
    扭矩限制器和驱动器的自动功率控制

    公开(公告)号:US20140079246A1

    公开(公告)日:2014-03-20

    申请号:US13622170

    申请日:2012-09-18

    摘要: Systems and methods are disclosed to provide automatic power control for a driver circuit. Embodiments disclosed herein enable a driver circuit to automatically decrease the gain of amplified input signals when output power exceeds a threshold. Further, embodiments disclosed herein enable a driver circuit to automatically increase the gain of amplified input signals when battery supply voltage drops to avoid unwanted output signal distortion. By using reference signals for battery power and amplified signal input, the amplifiers of the driver circuit can be automatically adjusted until an equilibrium is reached.

    摘要翻译: 公开了系统和方法来为驱动器电路提供自动功率控制。 当输出功率超过阈值时,本文公开的实施例使得驱动器电路能够自动降低放大的输入信号的增益。 此外,本文公开的实施例使得当电池电源电压下降时,驱动器电路自动地增加放大的输入信号的增益,以避免不期望的输出信号失真。 通过使用电池电源和放大信号输入的参考信号,可以自动调节驱动电路的放大器,直到达到平衡。

    Filterless class-D speaker driver with less switching
    9.
    发明申请
    Filterless class-D speaker driver with less switching 有权
    无滤波D类扬声器驱动器,切换少

    公开(公告)号:US20080265989A1

    公开(公告)日:2008-10-30

    申请号:US11797037

    申请日:2007-04-30

    申请人: Minsheng Wang

    发明人: Minsheng Wang

    IPC分类号: H03F3/217

    摘要: Methods for designing a filterless class-D amplifier and driver are described herein. In the exemplary embodiment, a feedback loop is used to stabilize the filterless class-D amplifier. A pulse width modulated (PWM) output signal is generated by adding a comparator input signal to a comparative signal, and comparing the sum to a peak voltage, which can be a peak value of the comparative signal. A limit of one PWM sample will be generated half per period of the comparative signal, resulting in lower dynamic switching noise and a decreased sensitivity to jitter noise than conventional filterless class-D amplifiers.

    摘要翻译: 本文描述了设计无滤波D类放大器和驱动器的方法。 在示例性实施例中,使用反馈环来稳定无滤波D类放大器。 通过将比较器输入信号与比较信号相加,并将该和与峰值电压进行比较,产生脉冲宽度调制(PWM)输出信号,峰值电压可以是比较信号的峰值。 一个PWM采样的限制将在比较信号的每个周期产生一半,导致比传统的无滤波D类放大器更低的动态开关噪声和对抖动噪声的灵敏度降低。

    Hardware-efficient implementation of dynamic element matching in sigma-delta DAC's
    10.
    发明授权
    Hardware-efficient implementation of dynamic element matching in sigma-delta DAC's 失效
    在Σ-ΔDAC中实现动态元件匹配的高效实现

    公开(公告)号:US06795003B2

    公开(公告)日:2004-09-21

    申请号:US10354159

    申请日:2003-01-30

    IPC分类号: H03M300

    摘要: A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0′, x1′} such that a number of 1's at bit x0′ over time is within ±1 of a number of 1's at bit x1′. At least two 4-bit vector shufflers input the vectors {x0′, x1′}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0′, x1′} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0′, x1′} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.

    摘要翻译: 用于混洗输入比特的数据洗牌装置包括多个比特洗牌器,每个比特混洗器输入相应的输入比特的两个比特x0和x1,并输出一个向量{x0',x1'},使得随着时间的推移,比特x0' 在位x1'的1的1的±1之内。 至少两个4位向量混洗器输入向量{x0',x1'}和输出4位向量,每个4位向量对应于由位产生的对应的两个向量{x0',x1'}的组合 使得4位向量混洗器以与位混合器对位x0和x1进行操作相同的方式对矢量{x0',x1'}进行操作。 基于4位向量洗牌器的下一个状态来更新位洗牌器的当前状态。