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130 条记录 (耗时 0.031 秒)

    METHOD AND SYSTEM FOR REDUCING VIA STUB RESONANCE
    31.
    发明申请
    METHOD AND SYSTEM FOR REDUCING VIA STUB RESONANCE 审中-公开
    通过STUB共鸣减少的方法和系统

    公开(公告)号：US20090049414A1

    公开(公告)日：2009-02-19

    申请号：US11840075

    申请日：2007-08-16

    申请人： Bhyrav M. MUTNURY ,  Moises Cases ,  Wallace G. Tuten ,  Erdem Matoglu

    发明人： Bhyrav M. MUTNURY ,  Moises Cases ,  Wallace G. Tuten ,  Erdem Matoglu

    IPC分类号： G06F17/50 ,  H05K1/11

    CPC分类号： H05K3/0005 ,  G06F17/5068 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09636

    摘要： Reducing via stub resonance in printed circuit boards. In one aspect, a method for reducing via stub resonance in a circuit board includes determining that resonance exists for a signal to be transmitted through a signal via extending across a plurality of layers in the circuit board. The resonance is caused by a via stub of the signal via, the via stub extending past a layer connected to the signal via. A location is determined for a ground via to be placed relative to the signal via, the location of the ground via being determined based on reducing the resonance for the signal to be transmitted in the signal via.

    摘要翻译： 通过印刷电路板中的短截线减少。 在一个方面，一种用于减少电路板中的通路短路谐振的方法包括确定通过延伸穿过电路板中的多个层的通过信号传输的信号的共振。 谐振是由信号通孔的通孔短路引起的，通孔短路延伸通过与信号通孔连接的层。 确定相对于信号通路放置的地面通路的位置，基于通过减少在信号通道中要发送的信号的谐振来确定地面的位置。

    MULTI-PATH REDUNDANT ARCHITECTURE FOR FAULT TOLERANT FULLY BUFFERED DIMMS
    36.
    发明申请
    MULTI-PATH REDUNDANT ARCHITECTURE FOR FAULT TOLERANT FULLY BUFFERED DIMMS 审中-公开
    多路径冗余架构，用于故障的全面缓冲区

    公开(公告)号：US20080155149A1

    公开(公告)日：2008-06-26

    申请号：US11613363

    申请日：2006-12-20

    申请人： Daniel N. de Araujo ,  Moises Cases ,  Erdem Matoglu ,  Nam H. Pham

    发明人： Daniel N. de Araujo ,  Moises Cases ,  Erdem Matoglu ,  Nam H. Pham

    IPC分类号： G06F13/16

    CPC分类号： G06F11/2007

    摘要： The present invention is directed to a multi-path redundant architecture for fault tolerant fully buffered dual inline memory modules (FB-DIMMs). The architecture includes: a FB-DIMM channel including a plurality of DIMM modules and a memory controller; a bidirectional serial memory bus for coupling the memory controller and the plurality of DIMM modules of the FB-DIMM channel in a first connection order; and a redundant bidirectional serial memory bus for coupling the memory controller and the plurality of DIMM modules of the FB-DIMM channel in a second connection order

    摘要翻译： 本发明涉及用于容错全缓冲双列直插式存储器模块（FB-DIMM）的多路径冗余架构。 该架构包括：包括多个DIMM模块的FB-DIMM通道和存储器控制器; 用于以第一连接顺序耦合存储器控制器和FB-DIMM通道的多个DIMM模块的双向串行存储器总线; 以及用于以第二连接顺序耦合存储器控制器和FB-DIMM通道的多个DIMM模块的冗余双向串行存储器总线

    Testing an electrical component
    37.
    发明授权
    Testing an electrical component 有权
    测试电气部件

    公开(公告)号：US08106666B2

    公开(公告)日：2012-01-31

    申请号：US12402806

    申请日：2009-03-12

    申请人： Rubina F. Ahmed ,  Moises Cases ,  Bradley D. Herrman ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Peter R. Seidel

    发明人： Rubina F. Ahmed ,  Moises Cases ,  Bradley D. Herrman ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Peter R. Seidel

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2806 ,  G01R15/183

    摘要： Testing an electrical component, the component including a printed circuit board (‘PCB’) with a number of traces, the traces organized in pairs with each trace of a pair carrying current in opposite directions and separated from one another by a substrate layer of the PCB, where testing of the electrical component includes: dynamically and iteratively until a present impedance for a pair of traces of the component is greater than a predetermined threshold impedance: increasing, by an impedance varying device at the behest of a testing device, magnetic field strength of a magnetic field applied to the pair of traces by the impedance varying device, including increasing the present impedance of the pair of traces; measuring, by the testing device, one or more operating parameters; and recording, by the testing device, the measurements of the operating parameters.

    摘要翻译： 测试电气部件，该部件包括具有多个迹线的印刷电路板（“PCB”），该迹线与成对的每个迹线成对地沿着相反的方向承载电流，并且彼此分离由基底层 PCB，其中电气部件的测试包括：动态地和迭代地，直到组件的一对迹线的当前阻抗大于预定阈值阻抗：通过测试装置的阻抗改变装置增加磁场 通过阻抗变化装置施加到该对迹线的磁场的强度，包括增加该对迹线的当前阻抗; 由所述测试装置测量一个或多个操作参数; 并由测试装置记录操作参数的测量值。

    Testing An Electrical Component
    38.
    发明申请
    Testing An Electrical Component 有权
    测试电气部件

    公开(公告)号：US20100231209A1

    公开(公告)日：2010-09-16

    申请号：US12402806

    申请日：2009-03-12

    申请人： Rubina F. Ahmed ,  Moises Cases ,  Bradley D. Herrman ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Peter R. Seidel

    发明人： Rubina F. Ahmed ,  Moises Cases ,  Bradley D. Herrman ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Peter R. Seidel

    IPC分类号： G01R31/00

    CPC分类号： G01R31/2806 ,  G01R15/183

    摘要： Testing an electrical component, the component including a printed circuit board (‘PCB’) with a number of traces, the traces organized in pairs with each trace of a pair carrying current in opposite directions and separated from one another by a substrate layer of the PCB, where testing of the electrical component includes: dynamically and iteratively until a present impedance for a pair of traces of the component is greater than a predetermined threshold impedance: increasing, by an impedance varying device at the behest of a testing device, magnetic field strength of a magnetic field applied to the pair of traces by the impedance varying device, including increasing the present impedance of the pair of traces; measuring, by the testing device, one or more operating parameters; and recording, by the testing device, the measurements of the operating parameters.

    摘要翻译： 测试电气部件，该部件包括具有多个迹线的印刷电路板（“PCB”），该迹线与成对的每个迹线成对地沿着相反的方向承载电流，并且彼此分离由基底层 PCB，其中电气部件的测试包括：动态地和迭代地，直到组件的一对迹线的当前阻抗大于预定阈值阻抗：通过测试装置的阻抗改变装置增加磁场 通过阻抗变化装置施加到该对迹线的磁场的强度，包括增加该对迹线的当前阻抗; 由所述测试装置测量一个或多个操作参数; 并由测试装置记录操作参数的测量值。

    BUS ARCHITECTURE
    39.
    发明申请
    BUS ARCHITECTURE 审中-公开
    总线架构

    公开(公告)号：US20080301352A1

    公开(公告)日：2008-12-04

    申请号：US11757942

    申请日：2007-06-04

    申请人： P. Maurice Bland ,  Moises Cases ,  Jonathan R. Hinkle ,  Pravin Patel ,  Nam H. Pham

    发明人： P. Maurice Bland ,  Moises Cases ,  Jonathan R. Hinkle ,  Pravin Patel ,  Nam H. Pham

    IPC分类号： G06F13/40

    CPC分类号： G06F13/4086

    摘要： A system and method for implementing a bus. In one embodiment, the system includes a bus switch operative to couple to a bus, and a plurality of trace segments coupled to the bus switch, where the trace segments have different lengths. The bus switch is operative to connect one of the trace segments to the bus based on at least one system requirement, and the selected trace segment cancels signal reflections on the bus.

    摘要翻译： 一种用于实现总线的系统和方法。 在一个实施例中，系统包括可操作以耦合到总线的总线开关和耦合到总线开关的多个迹线段，其中迹线段具有不同的长度。 总线开关可以根据至少一个系统要求将一个跟踪段连接到总线，并且所选择的跟踪段取消总线上的信号反射。

    Cable for high speed data communications
    40.
    发明授权
    Cable for high speed data communications 有权

    公开(公告)号：US10141086B2

    公开(公告)日：2018-11-27

    申请号：US12628245

    申请日：2009-12-01

    申请人： Moises Cases ,  Vinh B. Lu ,  Bhyrav M. Mutnury

    发明人： Moises Cases ,  Vinh B. Lu ,  Bhyrav M. Mutnury

    IPC分类号： H01B7/00 ,  H01B11/20 ,  H01B11/10 ,  H01P3/06

    摘要： A cable for high speed data communications is provided. The cable includes a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer. The first inner conductor is substantially parallel to the second inner conductor and to a longitudinal axis. The cable includes a conductive shield wrapped around the first and second inner conductors, with an overlap of the conductive shield along and about the longitudinal axis. The overlap is aligned with a low current plane. The low current plane is substantially parallel to the first and second inner conductors, substantially equidistant from the first and second inner conductors, and substantially orthogonal to a plane including the first and second inner conductors.