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    System and method for common history pessimism relief during static timing analysis
    31.
    发明授权
    System and method for common history pessimism relief during static timing analysis 有权
    静态时序分析中共同历史悲观缓解的系统和方法

    公开(公告)号：US08141014B2

    公开(公告)日：2012-03-20

    申请号：US12538229

    申请日：2009-08-10

    申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

    发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： A system and method for adjustment of modeled timing data variation as a function of past state and/or switching history during static timing analysis. One illustrative embodiment may include inputting and asserting at least one of initial signal history bound and explicit device history bound constraints for at least one signal of a circuit design and evaluating for a segment processed during a forward propagation of block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted. The method may further include evaluating for the segment whether history bounds are downstream from a gating restriction, and processing a next segment until there are no further segments.

    摘要翻译： 一种用于在静态时序分析期间调整作为过去状态和/或切换历史的函数的建模定时数据变化的系统和方法。 一个说明性实施例可以包括输入和断言用于电路设计的至少一个信号的初始信号历史约束和显式设备历史约束约束中的至少一个，并且针对在基于块的静态时序分析的正向传播期间处理的段来评估是否有任何输入 对当前段的信号具有有界历史，至少一个传播和断言。 该方法可以进一步包括评估该段是否历史边界是在门控限制的下游，以及处理下一个段，直到没有进一步的段。

    SYSTEM AND METHOD FOR DEVICE HISTORY BASED DELAY VARIATION ADJUSTMENT DURING STATIC TIMING ANALYSIS
    32.
    发明申请
    SYSTEM AND METHOD FOR DEVICE HISTORY BASED DELAY VARIATION ADJUSTMENT DURING STATIC TIMING ANALYSIS 有权
    基于静态时序分析的基于设备历史的延迟变化调整系统与方法

    公开(公告)号：US20100318951A1

    公开(公告)日：2010-12-16

    申请号：US12484293

    申请日：2009-06-15

    申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

    发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/504 ,  G06F2217/84

    摘要： A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a relationship between the sources of variability and one or more bounded device histories. Then, inputting history bounds for at least one signal of the integrated circuit design, and computing and propagating history bounds through at least one first segment of the integrated circuit design to at least one signal of the integrated circuit design. Further, the method may include evaluating from at least one of the propagated history bounds, device history bounds for at least one second segment of the integrated circuit design, and based on the evaluated device history bounds, adjusting at least one of a value of the history based delay variability and propagation of timing.

    摘要翻译： 一种用于在集成电路设计的静态时序分析期间调整基于历史的延迟变化的系统和方法。 该方法可以包括通过延迟变异性的基于历史的组件的变异源获得信息，以及变异源与一个或多个有界设备历史之间的关系。 然后，为集成电路设计的至少一个信号输入历史界限，并且通过集成电路设计的至少一个第一段将集成电路设计的至少一个信号计算和传播历史界限。 此外，该方法可以包括从至少一个传播的历史界限评估集成电路设计的至少一个第二段的设备历史界限，以及基于所评估的设备历史界限，调整至少一个 基于历史的延迟变异性和时间传播。

    CHIP DESIGN AND FABRICATION METHOD OPTIMIZED FOR PROFIT
    34.
    发明申请
    CHIP DESIGN AND FABRICATION METHOD OPTIMIZED FOR PROFIT 有权
    芯片设计和优化方法优化

    公开(公告)号：US20100293512A1

    公开(公告)日：2010-11-18

    申请号：US12467326

    申请日：2009-05-18

    申请人： Nathan Buck ,  Howard H. Chen ,  James P. Eckhardt ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Susan K. Lichtensteiger ,  Chandramouli Visweswariah ,  Tad J. Wilder

    发明人： Nathan Buck ,  Howard H. Chen ,  James P. Eckhardt ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Susan K. Lichtensteiger ,  Chandramouli Visweswariah ,  Tad J. Wilder

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5031

    摘要： Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips.

    摘要翻译： 公开了一种计算机实现的方法，用于设计芯片以优化不同仓中的产量部分作为多个不同度量的函数，并进一步最大化所得到的芯片仓的利润潜力。 该方法分别计算联合概率分布（JPD），每个JPD是不同度量（例如，性能，功耗等）的函数。 基于JPD，生成相应的收益率曲线。 利润函数然后将所有这些度量（例如，绩效值，功耗值等）的值减小到公共利润分母（例如，指示可能与给定度量值相关联的利润的货币值）。 更具体地说，利润函数，尤其是货币价值可用于将各种收益率曲线组合成基于利润的收益率曲线，从中可以产生利润模型。 基于这种利润模型，可以对芯片设计进行改变，以便根据所有不同的指标（例如性能，功耗等）来优化产量，并进一步最大化所得芯片的利润潜力 。

    Chip design and fabrication method optimized for profit
    37.
    发明授权
    Chip design and fabrication method optimized for profit 有权
    芯片设计和制造方法优化利润

    公开(公告)号：US08086988B2

    公开(公告)日：2011-12-27

    申请号：US12467326

    申请日：2009-05-18

    申请人： Nathan Buck ,  Howard H. Chen ,  James P. Eckhardt ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Susan K. Lichtensteiger ,  Chandramouli Visweswariah ,  Tad J. Wilder

    发明人： Nathan Buck ,  Howard H. Chen ,  James P. Eckhardt ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Susan K. Lichtensteiger ,  Chandramouli Visweswariah ,  Tad J. Wilder

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5031

    摘要： Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips.

    摘要翻译： 公开了一种计算机实现的方法，用于设计芯片以优化不同仓中的产量部分作为多个不同度量的函数，并进一步最大化所得到的芯片仓的利润潜力。 该方法分别计算联合概率分布（JPD），每个JPD是不同度量（例如，性能，功耗等）的函数。 基于JPD，生成相应的收益率曲线。 利润函数然后将所有这些度量（例如，绩效值，功耗值等）的值减小到公共利润分母（例如，指示可能与给定度量值相关联的利润的货币值）。 更具体地说，利润函数，尤其是货币价值可用于将各种收益率曲线组合成基于利润的收益率曲线，从中可以生成利润模型。 基于这种利润模型，可以对芯片设计进行改变，以便根据所有不同的指标（例如性能，功耗等）来优化产量，并进一步最大化所得芯片的利润潜力 。