公开(公告)号：US20100237421A1

公开(公告)日：2010-09-23

申请号：US12702380

申请日：2010-02-09

申请人： Anthony I. Chou ,  Gregory G. Freeman ,  Kevin McStay ,  Shreesh Narasimha

发明人： Anthony I. Chou ,  Gregory G. Freeman ,  Kevin McStay ,  Shreesh Narasimha

IPC分类号： H01L27/06 ,  H01L21/70

CPC分类号： H01L21/28518 ,  H01L21/76829 ,  H01L29/66356 ,  H01L29/7391

摘要： A gated diode structure and a method for fabricating the gated diode structure use a relaxed liner that is derived from a stressed liner that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner. The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method.

摘要翻译： 门控二极管结构和用于制造门控二极管结构的方法使用从应力衬里导出的松弛衬垫，其通常用于与栅极二极管结构同时形成的场效应晶体管的上下文中。 复杂的衬垫与应力衬里的处理（例如离子注入处理）形成。 与使用反应离子蚀刻方法相比，轻松的衬垫与应力衬里相比提供了改进的门控二极管理想，没有任何门控二极管损坏，其可能发生在从选通二极管结构剥离应力衬垫的同时发生。

公开(公告)号：US07749822B2

公开(公告)日：2010-07-06

申请号：US11869271

申请日：2007-10-09

申请人： Gregory G. Freeman ,  William K. Henson

发明人： Gregory G. Freeman ,  William K. Henson

IPC分类号： H01L21/00 ,  H01L27/12

CPC分类号： H01L27/0629 ,  H01L21/28088 ,  H01L28/20 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

摘要： An integrated semiconductor device includes a resistor and an FET device formed from a stack of layers. The stack of layers includes a dielectric layer formed on a substrate; a metal conductor layer having lower electrical resistance formed on the dielectric layer; and a polysilicon layer formed on the metal conductor layer. A resistor stack is formed by patterning a portion of the original stack of layers into a resistor. An FET stack is formed from another portion of the original stack of layers. The FET stack is doped to form a gate electrode and the resistor stack is doped aside from the resistor portion thereof. Then terminals are formed at distal ends of the resistor in a doped portion of the polysilicon layer. Alternatively, the polysilicon layer is etched away from the resistor stack followed by forming terminals at distal ends of the metal conductor in the resistor stack.

摘要翻译： 集成半导体器件包括由一叠层形成的电阻器和FET器件。 层叠层包括在基板上形成的电介质层; 在电介质层上形成具有较低电阻的金属导体层; 以及形成在金属导体层上的多晶硅层。 通过将原始堆叠层的一部分图案化成电阻器形成电阻器堆叠。 FET堆叠由原始层叠层的另一部分形成。 掺杂FET堆叠以形成栅电极，并且电阻器堆叠从其电阻器部分被掺杂。 然后，端子形成在多晶硅层的掺杂部分中的电阻器的远端处。 或者，将多晶硅层从电阻器堆叠中蚀刻掉，然后在电阻器堆叠中的金属导体的远端形成端子。

公开(公告)号：US20090273040A1

公开(公告)日：2009-11-05

申请号：US12113462

申请日：2008-05-01

申请人： Qingqing Liang ,  Huilong Zhu ,  Gregory G. Freeman

发明人： Qingqing Liang ,  Huilong Zhu ,  Gregory G. Freeman

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7839 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/458 ,  H01L29/47 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78624

摘要： The present invention, in one embodiment, provides a semiconductor device including a semiconducting body including a schottky barrier region at a first end of the semiconducting body, a drain dopant region at the second end of the semiconducting body, and a channel positioned between the schottky barrier region and the drain dopant region. The semiconducting device may further include a gate structure overlying the channel of the semiconducting body. Further, a drain contact may be present to the drain dopant region of the semiconducting body, the drain contact being composed of a conductive material and in direct physical contact with a portion of a sidewall of the semiconducting body having a dimension that is less than a thickness of the semiconducting body in which the drain dopant region is positioned.

摘要翻译： 在一个实施例中，本发明提供一种半导体器件，其包括半导体本体的第一端包括肖特基势垒区的半导体器件，半导体本体的第二端处的漏极掺杂区域和位于肖特基 势垒区域和漏极掺杂剂区域。 半导体器件还可以包括覆盖半导体本体的沟道的栅极结构。 此外，漏极接触可以存在于半导体本体的漏极掺杂区域，漏极接触由导电材料构成，并且与半导体本体的侧壁的一部分直接物理接触，其尺寸小于 其中漏极掺杂剂区域位于其中的半导体的厚度。

公开(公告)号：US20090090977A1

公开(公告)日：2009-04-09

申请号：US11869271

申请日：2007-10-09

申请人： Gregory G. Freeman ,  William K. Henson

发明人： Gregory G. Freeman ,  William K. Henson

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L27/0629 ,  H01L21/28088 ,  H01L28/20 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

摘要： An integrated semiconductor device includes a resistor and an FET device formed from a stack of layers. The stack of layers includes a dielectric layer formed on a substrate; a metal conductor layer having lower electrical resistance formed on the dielectric layer; and a polysilicon layer formed on the metal conductor layer. A resistor stack is formed by patterning a portion of the original stack of layers into a resistor. An FET stack is formed from another portion of the original stack of layers. The FET stack is doped to form a gate electrode and the resistor stack is doped aside from the resistor portion thereof. Then terminals are formed at distal ends of the resistor in a doped portion of the polysilicon layer. Alternatively, the polysilicon layer is etched away from the resistor stack followed by forming terminals at distal ends of the metal conductor in the resistor stack.

摘要翻译： 集成半导体器件包括由一叠层形成的电阻器和FET器件。 层叠层包括在基板上形成的电介质层; 在电介质层上形成具有较低电阻的金属导体层; 以及形成在金属导体层上的多晶硅层。 通过将原始堆叠层的一部分图案化成电阻器形成电阻器堆叠。 FET堆叠由原始层叠层的另一部分形成。 掺杂FET堆叠以形成栅电极，并且电阻器堆叠从其电阻器部分被掺杂。 然后，端子形成在多晶硅层的掺杂部分中的电阻器的远端处。 或者，将多晶硅层从电阻器堆叠中蚀刻掉，然后在电阻器堆叠中的金属导体的远端形成端子。

公开(公告)号：US06667521B2

公开(公告)日：2003-12-23

申请号：US10283739

申请日：2002-10-29

申请人： David C. Ahlgren ,  Gregory G. Freeman ,  Feng Yi Huang ,  Adam D. Ticknor

发明人： David C. Ahlgren ,  Gregory G. Freeman ,  Feng Yi Huang ,  Adam D. Ticknor

IPC分类号： H01L2976

CPC分类号： H01L29/66287 ,  H01L21/8249 ,  H01L27/0623

摘要： A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

公开(公告)号：US06414371B1

公开(公告)日：2002-07-02

申请号：US09580130

申请日：2000-05-30

申请人： Gregory G. Freeman ,  Robert A. Groves ,  Jeffrey Johnson ,  Seshadri Subbanna ,  Richard P. Volant

发明人： Gregory G. Freeman ,  Robert A. Groves ,  Jeffrey Johnson ,  Seshadri Subbanna ,  Richard P. Volant

IPC分类号： H01L27082

CPC分类号： H01L29/66242 ,  H01L21/8222 ,  H01L27/0823

摘要： High frequency performance of transistor designs is enhanced and manufacturing yield improved by removing and reducing sources of parasitic capacitance through combinations of processes from different technologies. After formation of collector, base and emitter regions on a substrate and attachment of a second substrate, the original substrate is wholly or partially removed, the inactive collector area is removed or rendered semi-insulating and wiring and contacts are made from the original back side of the chip. Dielectric material used in the manufacturing process can be removed to further reduce capacitance. The high frequency transistors can be bonded to CMOS chips or wafers to form BICMOS chips.

摘要翻译： 提高了晶体管设计的高频性能，并通过不同技术的工艺组合来去除和减少寄生电容源，从而提高了制造成品率。 在衬底上形成集电极，基极和发射极区域并附接第二衬底后，原始衬底被全部或部分去除，非活性集电极区域被去除或呈半绝缘，并且布线和接触由原始背面制成 的芯片。 可以去除在制造过程中使用的介电材料，以进一步降低电容。 高频晶体管可以结合到CMOS芯片或晶圆上以形成BICMOS芯片。

公开(公告)号：US08629501B2

公开(公告)日：2014-01-14

申请号：US13370898

申请日：2012-02-10

申请人： Huilong Zhu ,  Brian J. Greene ,  Dureseti Chidambarrao ,  Gregory G. Freeman

发明人： Huilong Zhu ,  Brian J. Greene ,  Dureseti Chidambarrao ,  Gregory G. Freeman

IPC分类号： H01L27/12

CPC分类号： H01L29/0603 ,  H01L21/76224 ,  H01L29/1025 ,  H01L29/1054 ,  H01L29/84

摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

摘要翻译： 在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。 通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。 应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。 氧化硅材料沉积在深沟槽中，平坦化和凹陷。 去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。 应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

公开(公告)号：US20100330763A1

公开(公告)日：2010-12-30

申请号：US12493549

申请日：2009-06-29

申请人： Gregory G. Freeman ,  Shreesh Narasimha ,  Ning Su ,  Hasan M. Nayfeh ,  Nivo Rovedo ,  Werner A. Rausch ,  Jian Yu

发明人： Gregory G. Freeman ,  Shreesh Narasimha ,  Ning Su ,  Hasan M. Nayfeh ,  Nivo Rovedo ,  Werner A. Rausch ,  Jian Yu

IPC分类号： H01L21/336

CPC分类号： H01L21/823425 ,  H01L21/26586 ,  H01L21/823412 ,  H01L29/66492 ,  H01L29/66659

摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.

摘要翻译： 本发明提供了形成非对称场效应晶体管的方法。 该方法包括在半导体衬底的顶部上形成至少第一和第二栅极掩模叠层，其中第一和第二栅极掩模叠层至少分别包括第一和第二栅极掩模叠层的第一和第二栅极导体 分别具有顶表面，第一侧和第二侧，第二侧与第一侧相对; 以第一角度从第一和第二栅极掩模叠层的第一侧进行第一光晕注入，同时施加第一栅极掩模叠层以防止第一光晕注入到达第二晶体管的第一源极/漏极区域，其中 第一角度等于或大于预定值; 以及以第二角度从所述第一和第二栅极掩模叠层的第二侧执行第二光晕注入，从而在所述第二晶体管的第二源极/漏极区域中产生晕轮注入，其中所述第一和第二角度是针对 与基底垂直。

公开(公告)号：US20100006926A1

公开(公告)日：2010-01-14

申请号：US12170687

申请日：2008-07-10

申请人： HUILONG ZHU ,  Xiaomeng Chen ,  Mahender Kumar ,  Brian J. Greene ,  Bachir Dirahoui ,  Jay W. Strane ,  Gregory G. Freeman

发明人： HUILONG ZHU ,  Xiaomeng Chen ,  Mahender Kumar ,  Brian J. Greene ,  Bachir Dirahoui ,  Jay W. Strane ,  Gregory G. Freeman

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/82385 ,  H01L21/823857

摘要： Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.

摘要翻译： 公开了在MOSFET中形成高性能栅极的方法及其结构。 一个实施例包括提供包括第一短沟道有源区，第二短沟道有源区和长沟道有源区的衬底的方法，每个有源区通过浅沟槽隔离（STI）与另一个分离。 以及在所述长沟道有源区上形成具有多晶硅栅极的场效应晶体管（FET），在所述第一短沟道有源区上具有第一功函数调节材料的第一双金属栅极FET和具有第二双金属栅极FET的第二双金属栅极FET， 第二短通道有源区域上的功函数调整材料，其中第一和第二功函数调节材料不同。

公开(公告)号：US07611953B2

公开(公告)日：2009-11-03

申请号：US11677776

申请日：2007-02-22

申请人： David C. Ahlgren ,  Gregory G. Freeman ,  Francois Pagette ,  Christopher M. Schnabel ,  Anna W. Topol

发明人： David C. Ahlgren ,  Gregory G. Freeman ,  Francois Pagette ,  Christopher M. Schnabel ,  Anna W. Topol

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.

摘要翻译： 双极晶体管具有通过金属化直接接触基极 - 集电极结下方的集电极，以降低集电极电阻。 消除了常规的通孔和掩埋层以及它们的相关电阻。 晶体管非常隔离，几乎消除了良好的衬底电容和器件到器件的漏电流。 该结构提供了改进的电气性能，包括改进的fT，Fmax和驱动电流。