摘要:
Systems and methods are disclosed for video processing modules. More specifically a network is disclosed for processing data. The network comprises a register DMA controller adapted to support register access and at least one node adapted to the data. At least one link communicates with the node, and is adapted to transmit data and at least one network module communicates with at least the link, and is adapted to route data to at least the link.
摘要:
Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data.
摘要:
A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.
摘要:
A system and method that abstracts an interrupt from a group of interrupts, which may occur in a module, to call another module. Abstracting one interrupt from a group of interrupts allows the called module to deal with only one interrupt. The choice of the interrupt may be based on the configuration of the module from which the interrupts are originated. In an embodiment of the present invention, the abstracted interrupt triggers an event. When the triggered event is completed, an interrupt may be fired off to the target module. An interrupt handler in the target module or an external interrupt handler may handle the interrupt that calls the target module.
摘要:
Provided is an architecture for a cryptography accelerator chip that allows significant performance improvements over previous prior art designs. In various embodiments, the architecture enables parallel processing of packets through a plurality of cryptography engines and includes a classification engine configured to efficiently process encryption/decryption of data packets. Cryptography acceleration chips in accordance may be incorporated on network line cards or service modules and used in applications as diverse as connecting a single computer to a WAN, to large corporate networks, to networks servicing wide geographic areas (e.g., cities). The present invention provides improved performance over the prior art designs, with much reduced local memory requirements, in some cases requiring no additional external memory. In some embodiments, the present invention enables sustained full duplex Gigabit rate security processing of IPSec protocol data packets.
摘要:
A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.
摘要:
A system and method that produces a spatial average for interlaced video in a deinterlacer. The system detects edges in the video images and determines the angle at which the edges are oriented based on the gradient in the x-direction and the gradient in the y-direction. The direction of the edge is determined using the angle information of the edge. The system may also determine the strength of the edge. Based on the determined characteristics of the edge a filter may be selected to produce a spatial average of the edge in the image.
摘要:
Computer-implemented methods and systems for creating and managing website content involve, for example, providing a user at a computer terminal a data capture template for a user-selected content type, providing the user at the computer terminal presentation pages using content management tags, allowing the user at the computer terminal to author content using the data capture template, and allowing the user at the computer terminal to deploy the content to a server. Other aspects of the methods and systems for creating and managing website content include, for example, allowing the user to personalize content, allowing the user to embed dynamic content in the middle of static content, allowing the user to refresh the deployed content in real-time without impacting current existing user sessions on the server where content is being deployed.
摘要:
Processing video signals may comprise converting interlaced formatted video to progressive scan video by simultaneously performing: color edge detection on a first and second field; temporal filtering on the second field and third field; and 3:2 pull down detecting on the second field and the third field. A bound output may be generated by binding an output from the color edge detecting and are output from the temporal filtering.
摘要:
Methods and apparatus are provided for efficiently normalizing and denormalizing data for cryptography processing. The normalization and denormalization techniques can be applied in the context of a cryptography accelerator coupled with a processor. Hardware normalization techniques are applied to data prior to cryptography processing. Context circuitry tracks the shift amount used for normalization. After cryptography processing, the processed data is denormalized using the shift amount tracked by the context circuitry.