Leakage Current Mitigation in a Semiconductor Device
    31.
    发明申请
    Leakage Current Mitigation in a Semiconductor Device 有权
    半导体器件漏电流减轻

    公开(公告)号:US20100327958A1

    公开(公告)日:2010-12-30

    申请号:US12494460

    申请日:2009-06-30

    IPC分类号: H03K3/01 G01R31/26

    CPC分类号: H03K17/0822

    摘要: A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels. This alert signal switches the target semiconductor device to an active mode for leakage mitigation, which includes a repair voltage from a repair voltage generator applied to the gate of the target semiconductor device.

    摘要翻译: 识别泄漏电流目标单元内的休眠模式目标半导体器件,以减轻漏电流,防止其达到灾难性的失控。 泄漏电流移动监视器单元电连接到泄漏电流目标单元的输出节点,并在两个连续的预定义时间周期内从所选择的目标半导体器件收集泄漏电流,并测量所收集的漏电流之间的差异。 比较器接收并比较当前移位监视器单元和参考电压发生器的输出。 当从泄漏电流移动监视器单元输出的泄漏电压超过参考电压时,比较器将报警信号传播到泄漏电流目标单元,表示泄漏电流即将接近灾难性失控水平的条件。 该警报信号将目标半导体器件切换到用于泄漏减轻的活动模式,其包括施加到目标半导体器件的栅极的修复​​电压发生器的修复电压。

    Active inductor for ASIC application
    34.
    发明授权
    Active inductor for ASIC application 有权
    有源电感用于ASIC应用

    公开(公告)号:US08115575B2

    公开(公告)日:2012-02-14

    申请号:US12191519

    申请日:2008-08-14

    IPC分类号: H03H11/00

    CPC分类号: H03H11/08 H03H11/48

    摘要: An apparatus and method for manufacturing low-cost high-density compact active inductor module using existing DRAM, SRAM and logic process integration. The elements of the active inductor modules are formed by three semiconductor devices including nMOS devices, deep-trench capacitors and a polysilicon or TaN resistor. The active inductor modules can be connected in a parallel and/or serial configuration to obtain a wide range of inductance values. The modular active inductors can be advantageously stored in an ASIC library to facilitate a flexible and convenient circuit design.

    摘要翻译: 一种使用现有DRAM,SRAM和逻辑处理集成制造低成本高密度紧凑型有源电感模块的装置和方法。 有源电感器模块的元件由包括nMOS器件,深沟槽电容器和多晶硅或TaN电阻器的三个半导体器件形成。 有源电感模块可以并联和/或串联配置连接,以获得宽范围的电感值。 模块化有源电感器可以有利地存储在ASIC库中,以便于灵活和方便的电路设计。

    Leakage current mitigation in a semiconductor device
    36.
    发明授权
    Leakage current mitigation in a semiconductor device 有权
    半导体器件中泄漏电流的减轻

    公开(公告)号:US07911263B2

    公开(公告)日:2011-03-22

    申请号:US12494460

    申请日:2009-06-30

    IPC分类号: G05F1/10 G01R31/26

    CPC分类号: H03K17/0822

    摘要: A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels. This alert signal switches the target semiconductor device to an active mode for leakage mitigation, which includes a repair voltage from a repair voltage generator applied to the gate of the target semiconductor device.

    摘要翻译: 识别泄漏电流目标单元内的休眠模式目标半导体器件,以减轻漏电流,防止其达到灾难性的失控。 泄漏电流移动监视器单元电连接到泄漏电流目标单元的输出节点,并在两个连续的预定义时间周期内从所选择的目标半导体器件收集泄漏电流,并测量所收集的漏电流之间的差异。 比较器接收并比较当前移位监视器单元和参考电压发生器的输出。 当从泄漏电流移动监视器单元输出的泄漏电压超过参考电压时,比较器将报警信号传播到泄漏电流目标单元,表示泄漏电流即将接近灾难性失控水平的条件。 该警报信号将目标半导体器件切换到用于泄漏减轻的活动模式,其包括施加到目标半导体器件的栅极的修复​​电压发生器的修复电压。

    Method and apparatus for extending the lifetime of a semiconductor chip
    37.
    发明授权
    Method and apparatus for extending the lifetime of a semiconductor chip 失效
    延长半导体芯片寿命的方法和装置

    公开(公告)号:US07821330B2

    公开(公告)日:2010-10-26

    申请号:US12045974

    申请日:2008-03-11

    IPC分类号: G05F1/10

    CPC分类号: G05F1/56

    摘要: A circuit and a method for extending the lifetime of a semiconductor chip. The circuit including a voltage reference generator, a voltage switch, a threshold voltage regulator device and a threshold voltage monitor device tunes an automatic internal power supply. The voltage reference generator provides one or more reference voltage levels that are transmitted to the voltage switch. The threshold voltage monitor device monitors the threshold voltage of the device, triggering the voltage switch to select a reference level for use as a voltage reference for the regulator when the threshold voltage of the monitored device exceeds a predetermined value. The regulator then converts the external power supply to an internal supply and holds it at the predetermined reference level.

    摘要翻译: 一种用于延长半导体芯片寿命的电路和方法。 包括电压基准发生器,电压开关,阈值电压调节器装置和阈值电压监视器装置的电路调谐自动内部电源。 电压参考发生器提供一个或多个传输到电压开关的参考电压电平。 阈值电压监视器件监视器件的阈值电压,当被监视器件的阈值电压超过预定值时,触发电压开关选择参考电平,以用作调节器的电压基准。 调节器然后将外部电源转换为内部电源并将其保持在预定的参考电平。

    ACTIVE INDUCTOR FOR ASIC APPLICATION
    38.
    发明申请
    ACTIVE INDUCTOR FOR ASIC APPLICATION 有权
    用于ASIC应用的主动电感器

    公开(公告)号:US20100039191A1

    公开(公告)日:2010-02-18

    申请号:US12191519

    申请日:2008-08-14

    IPC分类号: H03H11/48

    CPC分类号: H03H11/08 H03H11/48

    摘要: An apparatus and method for manufacturing low-cost high-density compact active inductor module using existing DRAM, SRAM and logic process integration. The elements of the active inductor modules are formed by three semiconductor devices including nMOS devices, deep-trench capacitors and a polysilicon or TaN resistor. The active inductor modules can be connected in a parallel and/or serial configuration to obtain a wide range of inductance values. The modular active inductors can be advantageously stored in an ASIC library to facilitate a flexible and convenient circuit design.

    摘要翻译: 一种使用现有DRAM,SRAM和逻辑处理集成制造低成本高密度紧凑型有源电感模块的装置和方法。 有源电感器模块的元件由包括nMOS器件,深沟槽电容器和多晶硅或TaN电阻器的三个半导体器件形成。 有源电感模块可以并联和/或串联配置连接,以获得宽范围的电感值。 模块化有源电感器可以有利地存储在ASIC库中,以便于灵活和方便的电路设计。

    Method and Apparatus for Extending the Lifetime of a Semiconductor Chip
    39.
    发明申请
    Method and Apparatus for Extending the Lifetime of a Semiconductor Chip 失效
    用于延长半导体芯片寿命的方法和装置

    公开(公告)号:US20090231025A1

    公开(公告)日:2009-09-17

    申请号:US12045974

    申请日:2008-03-11

    IPC分类号: G05F1/46

    CPC分类号: G05F1/56

    摘要: A circuit and a method for extending the lifetime of a semiconductor chip. The circuit including a voltage reference generator, a voltage switch, a threshold voltage regulator device and a threshold voltage monitor device tunes an automatic internal power supply. The voltage reference generator provides one or more reference voltage levels that are transmitted to the voltage switch. The threshold voltage monitor device monitors the threshold voltage of the device, triggering the voltage switch to select a reference level for use as a voltage reference for the regulator when the threshold voltage of the monitored device exceeds a predetermined value. The regulator then converts the external power supply to an internal supply and holds it at the predetermined reference level.

    摘要翻译: 一种用于延长半导体芯片寿命的电路和方法。 包括电压基准发生器,电压开关,阈值电压调节器装置和阈值电压监视器装置的电路调谐自动内部电源。 电压参考发生器提供一个或多个传输到电压开关的参考电压电平。 阈值电压监视器件监视器件的阈值电压,当被监视器件的阈值电压超过预定值时,触发电压开关选择参考电平,以用作调节器的电压基准。 调节器然后将外部电源转换为内部电源并将其保持在预定的参考电平。

    METHOD OF AND STRUCTURE FOR RECOVERING GAIN IN A BIPOLAR TRANSISTOR
    40.
    发明申请
    METHOD OF AND STRUCTURE FOR RECOVERING GAIN IN A BIPOLAR TRANSISTOR 有权
    在双极晶体管中恢复增益的方法和结构

    公开(公告)号:US20110128069A1

    公开(公告)日:2011-06-02

    申请号:US12627282

    申请日:2009-11-30

    IPC分类号: H03K3/01

    CPC分类号: H03F1/302

    摘要: A method of recovering gain in a bipolar transistor includes: providing a bipolar transistor including an emitter, a collector, and a base disposed between junctions at the emitter and the collector; reverse biasing the junction disposed between the emitter and the base with an operational voltage and for an operational time period, so that a current gain β of the transistor is degraded; idling the transistor, and generating a repair current Ibr into the base, while forward biasing the junction disposed between the emitter and the base with a first repair voltage (VEBR), and while at least partly simultaneously reverse biasing the junction disposed between the collector and the base with a second repair voltage (VCBR), for a repair time period (TR), so that the gain is at least party recovered; wherein VEBR, VCBR and TR have the proportional relationship: TR ∝ (Δβ)2×exp [1/(Tam+Rth×1e×VCER], VCER=VBER+VCBR, and 1e=β×Ibr, β is the normal current gain of the transistor, Δβ is the target recovery gain of the transistor in percentage, Tam is the ambient temperature in degrees K, Ibr is the repair current to the base in μ amps, Rth is the self-heating thermal resistance of the transistor in K/W, TR is in seconds. The invention further includes structures for implementing the method.

    摘要翻译: 一种在双极晶体管中恢复增益的方法,包括:提供一个包括发射极,集电极和设置在发射极和集电极之间的结之间的基极的双极晶体管; 使用工作电压和工作时间周期反向偏置设置在发射极和基极之间的结,使得电流增益&bgr; 的晶体管劣化; 使晶体管怠速,并产生修复电流Ibr到基极,同时以第一修复电压(VEBR)向前偏置设置在发射极和基极之间的结,并且至少部分地同时反向偏置设置在集电极和 具有第二修复电压(VCBR)的基座,用于修复时间段(TR),使得增益至少被回收; 其中VEBR,VCBR和TR具有比例关系:TRα(&Dgr;&bgr;)2×exp [1 /(Tam + Rth×1e×VCER),VCER = VBER + VCBR和1e =&bgr;×Ibr,&bgr ;晶体管的正常电流增益&Dgr;是晶体管的目标恢复增益百分比,谭是以K为单位的环境温度,Ibr是以μ安培为基准的修复电流,Rth是自 晶体管的热阻为K / W,TR为秒。本发明还包括实现该方法的结构。