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公开(公告)号:US09159597B2
公开(公告)日:2015-10-13
申请号:US13471583
申请日:2012-05-15
申请人: Chih-Tien Chang , Sunny Wu , Jo Fei Wang , Jong-I Mou , Chin-Hsiang Lin
发明人: Chih-Tien Chang , Sunny Wu , Jo Fei Wang , Jong-I Mou , Chin-Hsiang Lin
CPC分类号: H01L22/26 , H01L21/324 , H01L21/67115 , H01L21/67248 , H05B1/0233
摘要: An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer processing chamber. The apparatus further includes radiant heating elements disposed in different zones and operable to heat different portions of a wafer located within the wafer processing chamber. The apparatus further includes sensors disposed outside the wafer processing chamber and operable to monitor energy from the radiant heating elements disposed in the different zones. The apparatus further includes a computer configured to utilize the sensors to characterize the radiant heating elements disposed in the different zones and to provide a calibration for the radiant heating elements disposed in the different zones such that a substantially uniform temperature profile is maintained across a surface of the wafer.
摘要翻译: 公开了一种装置,系统和方法。 示例性装置包括晶片处理室。 该设备还包括设置在不同区域中的辐射加热元件,其可操作以加热位于晶片处理室内的晶片的不同部分。 该装置还包括设置在晶片处理室外部的传感器,其可操作以监测来自设置在不同区域中的辐射加热元件的能量。 该装置还包括计算机,其被配置为利用传感器来表征设置在不同区域中的辐射加热元件,并且为放置在不同区域中的辐射加热元件提供校准,使得基本上均匀的温度分布保持在 晶圆。
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公开(公告)号:US20120239178A1
公开(公告)日:2012-09-20
申请号:US13048282
申请日:2011-03-15
申请人: Sunny Wu , Chun-Hsien Lin , Kun-Ming Chen , Dung-Yian Hsieh , Hui-Ru Lin , Jo Fei Wang , Jong-I Mou , I-Ching Chu
发明人: Sunny Wu , Chun-Hsien Lin , Kun-Ming Chen , Dung-Yian Hsieh , Hui-Ru Lin , Jo Fei Wang , Jong-I Mou , I-Ching Chu
IPC分类号: G06F19/00
CPC分类号: H01L22/20 , G01R31/2894 , H01L22/14
摘要: A method comprises computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests. Each regression model outputs a wafer yield measure as a function of a plurality of device performance variables. For each failure bin, sensitivity of the wafer yield measure to each of the plurality of device performance variables is determined, and the device performance variables are ranked with respect to sensitivity of the wafer yield measure. A subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other are selected. The wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables are combined, to provide a combined wafer yield measure. At least one new process parameter value is selected to effect a change in the one device performance variable, based on the combined wafer yield measure. The at least one new process parameter value is to be used to process at least one additional wafer.
摘要翻译: 一种方法包括基于在晶片电测试期间识别的多个故障来计算多个故障仓中的每一个的相应回归模型。 每个回归模型输出作为多个设备性能变量的函数的晶片产量测量。 对于每个故障仓,确定晶片产量测量对多个器件性能变量中的每一个的灵敏度,并且相对于晶片产量测量的灵敏度对器件性能变量进行排序。 选择具有最高排名并且彼此具有小于阈值相关性的设备性能变量的子集。 组合对应于所选择的设备性能变量子集之一的每个故障仓的晶片产量测量,以提供组合晶片产量测量。 选择至少一个新的过程参数值,以基于组合的晶片产量测量来实现一个器件性能变量的变化。 至少一个新的过程参数值将用于处理至少一个附加晶片。
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公开(公告)号:US20100248398A1
公开(公告)日:2010-09-30
申请号:US12412138
申请日:2009-03-26
申请人: Jo Fei Wang , Sunny Wu , Jong-I Mou
发明人: Jo Fei Wang , Sunny Wu , Jong-I Mou
IPC分类号: H01L21/66 , B05C11/00 , H01L21/306
CPC分类号: H01L21/6831 , H01L22/20 , H01L2924/0002 , Y10S438/909 , H01L2924/00
摘要: The present disclosure provides a semiconductor manufacturing method. The method includes performing a first process to a wafer; measuring the wafer for wafer data after the first process; securing the wafer on an E-chuck in a processing chamber; collecting sensor data from a sensor embedded in the E-chuck; adjusting clamping forces to the E-chuck based on the wafer data and the sensor data; and thereafter performing a second process to the wafer secured on the E-chuck in the processing chamber.
摘要翻译: 本发明提供一种半导体制造方法。 该方法包括对晶片执行第一处理; 在第一次处理之后测量晶片的晶片数据; 将晶片固定在处理室中的电子卡盘上; 从嵌入在E卡盘中的传感器收集传感器数据; 基于晶片数据和传感器数据调整到E型卡盘的夹紧力; 然后对固定在处理室中的E型卡盘上的晶片进行第二处理。
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公开(公告)号:US08685759B2
公开(公告)日:2014-04-01
申请号:US12938610
申请日:2010-11-03
申请人: Jo Fei Wang , Sunny Wu , Jong-I Mou
发明人: Jo Fei Wang , Sunny Wu , Jong-I Mou
IPC分类号: H01L21/66
CPC分类号: H01L21/6831 , H01L22/20 , H01L2924/0002 , Y10S438/909 , H01L2924/00
摘要: The present disclosure describes a semiconductor manufacturing apparatus. The apparatus includes a processing chamber designed to perform a process to a wafer; an electrostatic chuck (E-chuck) configured in the processing chamber and designed to secure the wafer, wherein the E-chuck includes an electrode and a dielectric feature formed on the electrode; a tuning structure designed to hold the E-chuck to the processing chamber by clamping forces, wherein the tuning structure is operable to dynamically adjust the clamping forces; a sensor integrated with the E-chuck and sensitive to the clamping forces; and a process control module for controlling the tuning structure to adjust the clamping forces based on pre-measurement data from the wafer and sensor data from the sensor.
摘要翻译: 本公开描述了一种半导体制造装置。 该设备包括设计成对晶片执行处理的处理室; 配置在所述处理室中并设计成固定所述晶片的静电卡盘(E卡盘),其中所述E卡盘包括形成在所述电极上的电极和电介质特征; 调谐结构,其被设计成通过夹紧力将所述E卡盘保持在所述处理室中,其中所述调谐结构可操作以动态地调节所述夹紧力; 与E型卡盘集成并对夹紧力敏感的传感器; 以及过程控制模块,用于基于来自晶片的预测量数据和来自传感器的传感器数据来控制调谐结构以调整夹紧力。
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公开(公告)号:US08452439B2
公开(公告)日:2013-05-28
申请号:US13048282
申请日:2011-03-15
申请人: Sunny Wu , Chun-Hsien Lin , Kun-Ming Chen , Dung-Yian Hsieh , Hui-Ru Lin , Jo Fei Wang , Jong-I Mou , I-Ching Chu
发明人: Sunny Wu , Chun-Hsien Lin , Kun-Ming Chen , Dung-Yian Hsieh , Hui-Ru Lin , Jo Fei Wang , Jong-I Mou , I-Ching Chu
CPC分类号: H01L22/20 , G01R31/2894 , H01L22/14
摘要: A method comprises computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests. Each regression model outputs a wafer yield measure as a function of a plurality of device performance variables. For each failure bin, sensitivity of the wafer yield measure to each of the plurality of device performance variables is determined, and the device performance variables are ranked with respect to sensitivity of the wafer yield measure. A subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other are selected. The wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables are combined, to provide a combined wafer yield measure. At least one new process parameter value is selected to effect a change in the one device performance variable, based on the combined wafer yield measure. The at least one new process parameter value is to be used to process at least one additional wafer.
摘要翻译: 一种方法包括基于在晶片电测试期间识别的多个故障来计算多个故障仓中的每一个的相应回归模型。 每个回归模型输出作为多个设备性能变量的函数的晶片产量测量。 对于每个故障仓,确定晶片产量测量对多个器件性能变量中的每一个的灵敏度,并且相对于晶片产量测量的灵敏度对器件性能变量进行排序。 选择具有最高排名并且彼此具有小于阈值相关性的设备性能变量的子集。 组合对应于所选择的设备性能变量子集之一的每个故障仓的晶片产量测量,以提供组合晶片产量测量。 选择至少一个新的过程参数值,以基于组合的晶片产量测量来实现一个器件性能变量的变化。 至少一个新的过程参数值将用于处理至少一个附加晶片。
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公开(公告)号:US08295965B2
公开(公告)日:2012-10-23
申请号:US12839014
申请日:2010-07-19
申请人: Sunny Wu , Yen-Di Tsen , Chun-Hsien Lin , Keung Hui , Jo Fei Wang , Jong-I Mou
发明人: Sunny Wu , Yen-Di Tsen , Chun-Hsien Lin , Keung Hui , Jo Fei Wang , Jong-I Mou
CPC分类号: G05B19/4187 , G05B19/042 , G05B19/41865 , G05B2219/2602 , G05B2219/32237 , G05B2219/32423 , G05B2219/45031 , G05B2219/50065 , Y02P90/20
摘要: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.
摘要翻译: 实施例是用于半导体处理控制的方法。 该方法包括基于处理的晶片的参数从多个处理阶段识别关键处理阶段,基于该参数来预测由密钥处理阶段处理的晶片的趋势以及多个处理阶段中的一些,以及调度 晶片转换为调谐处理阶段中的第一多个工具之一。 根据趋势确定第一组多个工具中的一个。
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