Device performance parmeter tuning method and system
    1.
    发明授权
    Device performance parmeter tuning method and system 有权
    设备性能参数调节方法和系统

    公开(公告)号:US08452439B2

    公开(公告)日:2013-05-28

    申请号:US13048282

    申请日:2011-03-15

    摘要: A method comprises computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests. Each regression model outputs a wafer yield measure as a function of a plurality of device performance variables. For each failure bin, sensitivity of the wafer yield measure to each of the plurality of device performance variables is determined, and the device performance variables are ranked with respect to sensitivity of the wafer yield measure. A subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other are selected. The wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables are combined, to provide a combined wafer yield measure. At least one new process parameter value is selected to effect a change in the one device performance variable, based on the combined wafer yield measure. The at least one new process parameter value is to be used to process at least one additional wafer.

    摘要翻译: 一种方法包括基于在晶片电测试期间识别的多个故障来计算多个故障仓中的每一个的相应回归模型。 每个回归模型输出作为多个设备性能变量的函数的晶片产量测量。 对于每个故障仓,确定晶片产量测量对多个器件性能变量中的每一个的灵敏度,并且相对于晶片产量测量的灵敏度对器件性能变量进行排序。 选择具有最高排名并且彼此具有小于阈值相关性的设备性能变量的子集。 组合对应于所选择的设备性能变量子集之一的每个故障仓的晶片产量测量,以提供组合晶片产量测量。 选择至少一个新的过程参数值,以基于组合的晶片产量测量来实现一个器件性能变量的变化。 至少一个新的过程参数值将用于处理至少一个附加晶片。

    DEVICE PERFORMANCE PARMETER TUNING METHOD AND SYSTEM
    2.
    发明申请
    DEVICE PERFORMANCE PARMETER TUNING METHOD AND SYSTEM 有权
    装置性能参数调节方法和系统

    公开(公告)号:US20120239178A1

    公开(公告)日:2012-09-20

    申请号:US13048282

    申请日:2011-03-15

    IPC分类号: G06F19/00

    摘要: A method comprises computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests. Each regression model outputs a wafer yield measure as a function of a plurality of device performance variables. For each failure bin, sensitivity of the wafer yield measure to each of the plurality of device performance variables is determined, and the device performance variables are ranked with respect to sensitivity of the wafer yield measure. A subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other are selected. The wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables are combined, to provide a combined wafer yield measure. At least one new process parameter value is selected to effect a change in the one device performance variable, based on the combined wafer yield measure. The at least one new process parameter value is to be used to process at least one additional wafer.

    摘要翻译: 一种方法包括基于在晶片电测试期间识别的多个故障来计算多个故障仓中的每一个的相应回归模型。 每个回归模型输出作为多个设备性能变量的函数的晶片产量测量。 对于每个故障仓,确定晶片产量测量对多个器件性能变量中的每一个的灵敏度,并且相对于晶片产量测量的灵敏度对器件性能变量进行排序。 选择具有最高排名并且彼此具有小于阈值相关性的设备性能变量的子集。 组合对应于所选择的设备性能变量子集之一的每个故障仓的晶片产量测量,以提供组合晶片产量测量。 选择至少一个新的过程参数值,以基于组合的晶片产量测量来实现一个器件性能变量的变化。 至少一个新的过程参数值将用于处理至少一个附加晶片。

    E-CHUCK WITH AUTOMATED CLAMPED FORCE ADJUSTMENT AND CALIBRATION
    7.
    发明申请
    E-CHUCK WITH AUTOMATED CLAMPED FORCE ADJUSTMENT AND CALIBRATION 有权
    具有自动钳位力调整和校准的电动自行车

    公开(公告)号:US20110042006A1

    公开(公告)日:2011-02-24

    申请号:US12938610

    申请日:2010-11-03

    摘要: The present disclosure describes a semiconductor manufacturing apparatus. The apparatus includes a processing chamber designed to perform a process to a wafer; an electrostatic chuck (E-chuck) configured in the processing chamber and designed to secure the wafer, wherein the E-chuck includes an electrode and a dielectric feature formed on the electrode; a tuning structure designed to hold the E-chuck to the processing chamber by clamping forces, wherein the tuning structure is operable to dynamically adjust the clamping forces; a sensor integrated with the E-chuck and sensitive to the clamping forces; and a process control module for controlling the tuning structure to adjust the clamping forces based on pre-measurement data from the wafer and sensor data from the sensor.

    摘要翻译: 本公开描述了一种半导体制造装置。 该设备包括设计成对晶片执行处理的处理室; 配置在所述处理室中并设计成固定所述晶片的静电卡盘(E卡盘),其中所述E卡盘包括形成在所述电极上的电极和电介质特征; 调谐结构,其被设计成通过夹紧力将所述E卡盘保持在所述处理室中,其中所述调谐结构可操作以动态地调节所述夹紧力; 与E型卡盘集成并对夹紧力敏感的传感器; 以及过程控制模块,用于基于来自晶片的预测量数据和来自传感器的传感器数据来控制调谐结构以调整夹紧力。

    Physical failure analysis guiding methods
    8.
    发明授权
    Physical failure analysis guiding methods 有权
    物理故障分析指导方法

    公开(公告)号:US08205173B2

    公开(公告)日:2012-06-19

    申请号:US12818003

    申请日:2010-06-17

    CPC分类号: G01R31/2894

    摘要: A method includes providing a plurality of failure dies, and performing a chip probing on the plurality of failure dies to generate a data log comprising electrical characteristics of the plurality of failure dies. An automatic net tracing is performed to trace failure candidate nodes in the failure dies. A failure layer analysis is performed on results obtained from the automatic net tracing. Physical failure analysis (PFA) samples are selected from the plurality of failure dies using results obtained in the step of performing the failure layer analysis.

    摘要翻译: 一种方法包括提供多个故障管芯,并对多个故障管芯进行芯片探测以产生包括多个故障管芯的电气特性的数据记录。 执行自动网络跟踪以跟踪故障模块中的故障候选节点。 对从自动网络跟踪获得的结果执行故障层分析。 使用在执行故障层分析的步骤中获得的结果从多个故障模具中选择物理故障分析(PFA)样本。

    Method for bin-based control
    10.
    发明授权
    Method for bin-based control 有权
    基于bin的控制方法

    公开(公告)号:US08041451B2

    公开(公告)日:2011-10-18

    申请号:US12427154

    申请日:2009-04-21

    摘要: A method for providing bin-based control when manufacturing integrated circuit devices is disclosed. The method comprises performing a plurality of processes on a plurality of wafer lots; determining a required bin quantity, an actual bin quantity, and a projected bin quantity; comparing the determined required bin quantity with the determined actual bin quantity and determined projected bin quantity; and modifying at least one of the plurality of processes on the plurality of wafer lots if the determined actual bin quantity and determined projected bin quantity fail to satisfy the determined required bin quantity.

    摘要翻译: 公开了一种在制造集成电路器件时提供基于bin的控制的方法。 该方法包括在多个晶片批次上执行多个处理; 确定所需的仓数量,实际箱数量和投影箱数量; 将确定的所需仓量与确定的实际箱数量和确定的预计仓量进行比较; 以及如果所确定的实际仓量和确定的投影箱数量不能满足所确定的所需仓量,则修改多个晶片批次上的多个处理中的至少一个。