公开(公告)号：US20150220475A1

公开(公告)日：2015-08-06

申请号：US14609488

申请日：2015-01-30

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Yossi Amon ,  Nir Gerber ,  Assaf Shacham

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/364 ,  G06F13/409 ,  G06F13/4282 ,  G06F13/4291 ,  H04L61/2038 ,  H04L61/2046 ,  H04L61/2092 ,  H04L61/3005

Abstract: Device identification generation in electronic devices to allow external control, such as selection or reprogramming, of device identification for bus communications identification, is disclosed. In this manner, device identifications of electronic devices coupled to a common communications bus in a system can be selected or reprogrammed to ensure they are unique to avoid bus communications collisions. In certain aspects, to select or reprogram a device identification in an electronic device, an external source can be electrically coupled to the electronic device. The external source closes a circuit with a device identification generation circuit in the electronic device. The closed circuit provides a desired electrical characteristic detectable by the device identification generation circuit. The device identification generation circuit is configured to generate a device identification as a function of the detected electrical characteristics of the closed circuit from the external source.

Abstract translation: 公开了用于允许外部控制（例如选择或重新编程）用于总线通信识别的设备标识的电子设备中的设备识别生成。 以这种方式，可以选择或重新编程耦合到系统中的公共通信总线的电子设备的设备标识，以确保它们是唯一的，以避免总线通信冲突。 在某些方面，为了在电子设备中选择或重新编程设备识别，外部源可以电耦合到电子设备。 外部源在电子设备中用设备识别生成电路闭合电路。 封闭电路提供了可由设备识别生成电路检测的期望的电特性。 设备识别生成电路被配置为根据检测到的来自外部源的闭路电气特性产生设备标识。

公开(公告)号：US20150074294A1

公开(公告)日：2015-03-12

申请号：US14478032

申请日：2014-09-05

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Tom Yahalom ,  Aviad Zacks-Shtrauss

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679 ,  G06F13/4243 ,  G06F2003/0697 ,  G06F2206/1014

Abstract: Providing command queuing in embedded memories is provided. In particular, aspects disclosed herein relate to a process through which a status of the queue is communicated to a host from a device. Aspects of the present disclosure use the command structure of the embedded Multi-Media Card (eMMC) standard, such that the host may determine a state of the queue in the device proximate a known end of an in-progress data transfer. In this manner, the host can select a task to commence after completion of a current data transfer while the current data transfer is still ongoing.

Abstract translation: 提供了嵌入式存储器中的命令排队。 特别地，本文公开的方面涉及将队列的状态从设备传送到主机的过程。 本公开的方面使用嵌入式多媒体卡（eMMC）标准的命令结构，使得主机可以在接近于正在进行的数据传输的已知结束的情况下确定设备中的队列的状态。 以这种方式，当当前的数据传送仍在进行时，主机可以选择完成当前数据传输之后开始的任务。

公开(公告)号：US20140281283A1

公开(公告)日：2014-09-18

申请号：US13798803

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Assaf Shacham ,  Amit Gil ,  Erez Tsidon ,  Yanru Li ,  Azzedine Touzni

IPC: G11C7/10

CPC classification number: G11C7/1075 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/462 ,  G06F9/463 ,  G06F9/52 ,  G06F9/544 ,  G06F11/0757 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

Abstract: Efficient techniques using a multi-port shared non-volatile memory are described that reduce latency in memory accesses from dedicated function specific processors, such as a modem control processor. The modem processor preempts a host processor that is accessing data from a multi-port shared non-volatile memory flash device allowing the modem processor to quickly access data in the flash device. The preemption process uses a doorbell interrupt initiated by a processor that seeks access and interrupts the processor being preempted. After preemption, the host processor may resume or restart the data access. Access control by the processors utilizes a hardware semaphore atomic control mechanism. Power control of the shared non-volatile memory modules includes at least one inactivity timer to indicate when a supply voltage to the shared non-volatile memory modules can be safely reduced or turned off. Power may be restarted by any of the processors sharing the memory, allowing fast access to the data.

Abstract translation: 描述了使用多端口共享非易失性存储器的有效技术，其减少了诸如调制解调器控制处理器之类的专用功能特定处理器的存储器访问中的延迟。 调制解调器处理器抢占正在从多端口共享非易失性存储器闪存器件访问数据的主处理器，允许调制解调器处理器快速访问闪存设备中的数据。 抢占过程使用由寻求访问并中断处理器被抢占的处理器发起的门铃中断。 抢占后，主机处理器可以恢复或重新启动数据访问。 处理器的访问控制利用硬件信号量原子控制机制。 共享的非易失性存储器模块的功率控制包括至少一个不活动定时器，以指示何时可以安全地减少或关闭共享的非易失性存储器模块的电源电压。 共享内存的任何处理器可能会重新启动电源，从而可以快速访问数据。