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29 条记录 (耗时 0.016 秒)

    Method and apparatus for virtualized control of a shared system cache
    1.
    发明授权
    Method and apparatus for virtualized control of a shared system cache 有权

    公开(公告)号：US10180908B2

    公开(公告)日：2019-01-15

    申请号：US14710693

    申请日：2015-05-13

    申请人： QUALCOMM Incorporated

    发明人： Yanru Li ,  Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Azzedine Touzni

    IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/0888 ,  G06F12/084 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/1045

    摘要： Aspects include computing devices, systems, and methods for implementing a cache maintenance or status operation for a component cache of a system cache. A computing device may generate a component cache configuration table, assign at least one component cache indicator of a component cache to a master of the component cache, and map at least one control register to the component cache indicator by a centralized control entity. The computing device may store the component cache indicator such that the component cache indicator is accessible by the master of the component cache for discovering a virtualized view of the system cache and issuing a cache maintenance or status command for the component cache bypassing the centralized control entity. The computing device may receive the cache maintenance or status command by a control register associated with a cache maintenance or status command and the component cache bypassing the centralized control entity.

    Secure, fast and normal virtual interrupt direct assignment in a virtualized interrupt controller in a mobile system-on-chip
    3.
    发明授权
    Secure, fast and normal virtual interrupt direct assignment in a virtualized interrupt controller in a mobile system-on-chip 有权
    安全，快速和正常的虚拟中断直接分配在移动片上系统的虚拟中断控制器中

    公开(公告)号：US09355050B2

    公开(公告)日：2016-05-31

    申请号：US14072201

    申请日：2013-11-05

    申请人： QUALCOMM Incorporated

    发明人： Thomas Zeng ,  Samar Asbe ,  Azzedine Touzni

    IPC分类号： G06F13/26 ,  G06F13/24 ,  G06F9/455 ,  G06F9/48

    CPC分类号： G06F13/26 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/4812 ,  G06F13/24 ,  G06F2009/45579

    摘要： Aspects include apparatuses and methods for secure, fast and normal virtual interrupt direct assignment managing secure and non-secure, virtual and physical interrupts by processor having a plurality of execution environments, including a trusted (secure) and a non-secure execution environment. An interrupt controller may identify a security group value for an interrupt and direct secure interrupts to the trusted execution environment. The interrupt controller may identify a direct assignment value for the non-secure interrupts indicating whether the non-secure interrupt is owned by a high level operating system (HLOS) Guest or a virtual machine manager (VMM), and whether it is a fast or a normal virtual interrupt. The interrupt controller may direct the HLOS Guest owned interrupt to the HLOS Guest while bypassing the VMM. When the HLOS Guest in unavailable, the interrupt may be directed to the VMM to attempt to pass the interrupt to the HLOS Guest until successful.

    摘要翻译： 方面包括用于安全，快速和正常的虚拟中断直接分配的装置和方法，其通过包括可信（安全）和非安全执行环境的多个执行环境的处理器管理安全和非安全的虚拟和物理中断。 中断控制器可以识别中断的安全组值，并将可靠执行环境直接安全中断。 中断控制器可以识别非安全中断的直接分配值，指示非安全中断是由高级操作系统（HLOS）来宾还是虚拟机管理器（VMM）拥有，以及它是快速还是快速 一个正常的虚拟中断。 在绕过VMM时，中断控制器可以将HLOS Guest拥有的中断指向HLOS Guest。 当HLOS访客不可用时，中断可能被定向到VMM，以尝试将中断传递给HLOS访客，直到成功。

    Dual host embedded shared device controller
    4.
    发明授权
    Dual host embedded shared device controller 有权
    双主机嵌入式共享设备控制器

    公开(公告)号：US09431077B2

    公开(公告)日：2016-08-30

    申请号：US13798803

    申请日：2013-03-13

    申请人： QUALCOMM Incorporated

    发明人： Assaf Shacham ,  Amit Gil ,  Erez Tsidon ,  Yanru Li ,  Azzedine Touzni

    IPC分类号： G06F9/52 ,  G06F9/54 ,  G11C7/10 ,  G06F1/32 ,  G06F9/46 ,  G06F11/07

    CPC分类号： G11C7/1075 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/462 ,  G06F9/463 ,  G06F9/52 ,  G06F9/544 ,  G06F11/0757 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

    摘要： Efficient techniques using a multi-port shared non-volatile memory are described that reduce latency in memory accesses from dedicated function specific processors, such as a modem control processor. The modem processor preempts a host processor that is accessing data from a multi-port shared non-volatile memory flash device allowing the modem processor to quickly access data in the flash device. The preemption process uses a doorbell interrupt initiated by a processor that seeks access and interrupts the processor being preempted. After preemption, the host processor may resume or restart the data access. Access control by the processors utilizes a hardware semaphore atomic control mechanism. Power control of the shared non-volatile memory modules includes at least one inactivity timer to indicate when a supply voltage to the shared non-volatile memory modules can be safely reduced or turned off. Power may be restarted by any of the processors sharing the memory, allowing fast access to the data.

    摘要翻译： 描述了使用多端口共享非易失性存储器的有效技术，其减少了诸如调制解调器控制处理器之类的专用功能特定处理器的存储器访问中的延迟。 调制解调器处理器抢占正在从多端口共享非易失性存储器闪存器件访问数据的主处理器，允许调制解调器处理器快速访问闪存设备中的数据。 抢占过程使用由寻求访问并中断处理器被抢占的处理器发起的门铃中断。 抢占后，主机处理器可以恢复或重新启动数据访问。 处理器的访问控制利用硬件信号量原子控制机制。 共享的非易失性存储器模块的功率控制包括至少一个不活动定时器，以指示何时可以安全地减少或关闭共享的非易失性存储器模块的电源电压。 共享内存的任何处理器可能会重新启动电源，从而可以快速访问数据。

    Distributed dynamic memory management unit (MMU)-based secure inter-processor communication
    6.
    发明授权
    Distributed dynamic memory management unit (MMU)-based secure inter-processor communication 有权
    基于分布式动态内存管理单元（MMU）的安全处理器间通信

    公开(公告)号：US09170957B2

    公开(公告)日：2015-10-27

    申请号：US14014288

    申请日：2013-08-29

    申请人： Qualcomm Incorporated

    发明人： Azzedine Touzni ,  Thomas Zeng

    IPC分类号： G06F12/14 ,  G06F12/10 ,  G06F15/167 ,  G06F21/60 ,  G06F21/79

    CPC分类号： G06F21/606 ,  G06F12/1009 ,  G06F12/1475 ,  G06F12/1483 ,  G06F15/167 ,  G06F21/76 ,  G06F21/79 ,  G06F2212/1052

    摘要： A first processor and a second processor are configured to communicate secure inter-processor communications (IPCs) with each other. The first processor effects secure IPCs and non-secure IPCs using a first memory management unit (MMU) to route the secure and non-secure IPCs via a memory system. The first MMU accesses a first page table stored in the memory system to route the secure IPCs and accesses a second page table stored in the memory system to route the non-secure IPCs. The second processor effects at least secure IPCs using a second MMU to route the secure IPCs via the memory system. The second MMU accesses the second page table to route the secure IPCs.

    摘要翻译： 第一处理器和第二处理器被配置为彼此通信安全的处理器间通信（IPC）。 第一个处理器使用第一个内存管理单元（MMU）通过内存系统对安全和非安全的IPC进行路由，从而影响安全的IPC和非安全的IPC。 第一MMU访问存储在存储器系统中的第一页表以路由安全的IPC并访问存储在存储器系统中的第二页表以路由非安全的IPC。 第二个处理器至少使用第二个MMU来保护安全的IPC，以便通过存储系统路由安全的IPC。 第二个MMU访问第二页表以路由安全的IPC。

    MEMORY ACCESS MANAGEMENT FOR LOW-POWER USE CASES OF A SYSTEM ON CHIP VIA SECURE NON-VOLATILE RANDOM ACCESS MEMORY
    8.
    发明申请
    MEMORY ACCESS MANAGEMENT FOR LOW-POWER USE CASES OF A SYSTEM ON CHIP VIA SECURE NON-VOLATILE RANDOM ACCESS MEMORY 审中-公开

    公开(公告)号：US20190129493A1

    公开(公告)日：2019-05-02

    申请号：US15798116

    申请日：2017-10-30

    申请人： QUALCOMM INCORPORATED

    发明人： YANRU LI ,  Azzedine Touzni ,  Dexter Tamio Chun

    IPC分类号： G06F1/32 ,  G06F9/44 ,  G06F15/78

    摘要： Systems and methods are disclosed for managing memory access for low-power use cases of a system on chip. One such method comprises booting a system on chip (SoC) comprising a plurality of SoC processing devices. A trusted channel is created to a secure non-volatile random access memory (NVRAM). The method determines a power-saving software program to be executed on the SoC by one of the plurality of SoC processing devices. A software image associated with the power-saving software program is loaded to the secure NVRAM. In response to loading the software image to the secure NVRAM, each of the plurality of SoC processing devices except the one executing the software image from the secure NVRAM are powered down.

    Methods and systems for reducing the amount of time and computing resources that are required to perform a hardware table walk (HWTW)
    9.
    发明授权
    Methods and systems for reducing the amount of time and computing resources that are required to perform a hardware table walk (HWTW) 有权
    用于减少执行硬件表行走所需的时间量和计算资源的方法和系统（HWTW）

    公开(公告)号：US09015400B2

    公开(公告)日：2015-04-21

    申请号：US13785877

    申请日：2013-03-05

    申请人： QUALCOMM Incorporated

    发明人： Thomas Zeng ,  Azzedine Touzni ,  Tzung Ren Tzeng ,  Phil J. Bostley

    IPC分类号： G06F12/02 ,  G06F12/10 ,  G06F9/455

    CPC分类号： G06F12/1027 ,  G06F9/45533 ,  G06F9/45545 ,  G06F9/45558 ,  G06F12/10 ,  G06F2212/151 ,  G06F2212/171 ,  G06F2212/507 ,  G06F2212/654 ,  G06F2212/684

    摘要： A computer system and a method are provided that reduce the amount of time and computing resources that are required to perform a hardware table walk (HWTW) in the event that a translation lookaside buffer (TLB) miss occurs. If a TLB miss occurs when performing a stage 2 (S2) HWTW to find the PA at which a stage 1 (S1) page table is stored, the MMU uses the IPA to predict the corresponding PA, thereby avoiding the need to perform any of the S2 table lookups. This greatly reduces the number of lookups that need to be performed when performing these types of HWTW read transactions, which greatly reduces processing overhead and performance penalties associated with performing these types of transactions.

    摘要翻译： 提供一种计算机系统和方法，其在发生翻译后备缓冲器（TLB）未命中的情况下减少执行硬件表行走（HWTW）所需的时间量和计算资源。 如果执行阶段2（S2）HWTW以找到存储第1（S1）页表的PA时发生TLB未命中，则MMU使用IPA来预测对应的PA，从而避免执行任何 S2表查找。 这大大减少了执行这些类型的HWTW读取事务时需要执行的查找次数，这大大降低了与执行这些类型的事务相关联的处理开销和性能损失。