公开(公告)号：US20170372989A1

公开(公告)日：2017-12-28

申请号：US15190164

申请日：2016-06-22

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Mario Francisco VELEZ ,  Changhan Hobie YUN ,  David Francis BERDY ,  Chengjie ZUO ,  Jonghae KIM

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/60 ,  H01L23/31

CPC classification number: H01L23/49805 ,  H01L21/4846 ,  H01L23/3121 ,  H01L23/49811 ,  H01L2021/60007 ,  H01L2224/081 ,  H01L2224/09155 ,  H01L2224/16113 ,  H01L2224/16225

Abstract: A device package with a reduced foot print may include a substrate and a through-substrate via extending from a top surface to a bottom surface of the substrate. The assembly may also include a trace and a contact pad on the top and bottom surfaces of the substrate and electrically coupled to the through-substrate via. An encapsulated die above the substrate may be electrically coupled to the trace. A joint below the substrate may be electrically coupled to the contact pad. A sidewall of the through-substrate via may be exposed. At least a portion of the through-substrate via may be within an outer side boundary of the substrate. Also, the trace and the contact pad may be within the outer side boundary of the substrate.

公开(公告)号：US20170288707A1

公开(公告)日：2017-10-05

申请号：US15088019

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  David Francis BERDY ,  Chengjie ZUO ,  Daeik Daniel KIM ,  Mario Francisco VELEZ ,  Niranjan Sunil MUDAKATTE ,  Robert Paul MIKULKA

IPC: H04B1/00 ,  H03H3/00 ,  H03H7/01

CPC classification number: H04B1/0057 ,  H01L2224/11 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/463 ,  H03H2001/0085

Abstract: A three dimensional (3D) multiplexer structure may include a first two dimensional (2D) inductor capacitor (LC) filter layer. The first 2D LC filter layer may include a first 2D spiral inductor and a first capacitor(s). The 3D multiplexer structure may also include a second 2D LC filter layer. The second 2D LC filter layer may include a second 2D spiral inductor and a second capacitor(s) stacked directly on and communicably coupled to the first 2D LC filter.

公开(公告)号：US20170187345A1

公开(公告)日：2017-06-29

申请号：US15067106

申请日：2016-03-10

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Daeik Daniel KIM ,  Mario Francisco VELEZ ,  Chengjie ZUO ,  David Francis BERDY ,  Jonghae KIM

IPC: H03H7/01 ,  H03H3/00 ,  H01P5/16 ,  H01Q1/50 ,  H01Q1/22

CPC classification number: H01P5/16 ,  H01Q1/22 ,  H01Q1/50 ,  H03H7/0115 ,  H03H7/463

Abstract: A multiplexer structure includes a passive substrate. The multiplexer structure may also include a high band filter on the passive substrate. The high band filter may include a 2D planar spiral inductor(s) on the passive substrate. The multiplexer structure may further include a low band filter on the passive substrate. The low band filter may include a 3D through-substrate inductor and a first capacitor(s) on the passive substrate. The multiplexer structure may also include a through substrate via(s) coupling the high band filter and the low band filter.

公开(公告)号：US20170178810A1

公开(公告)日：2017-06-22

申请号：US14976973

申请日：2015-12-21

Applicant: QUALCOMM Incorporated

Inventor： David Francis BERDY ,  Daeik Daniel KIM ,  Niranjan Sunil MUDAKATTE ,  Je-Hsiung Jeffrey LAN ,  Chengjie ZUO ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Jonghae KIM

IPC: H01G4/30 ,  H01G4/01

CPC classification number: H01G4/30 ,  H01G4/01 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/86 ,  H01L28/87 ,  H01L29/94

Abstract: An exemplary MIM capacitor may include a first metal plate, a dielectric layer on the first metal plate, a second metal plate on the dielectric layer, a via layer on the second metal plate, and a third metal plate on the via layer where the second metal plate has a tapered outline with a first side and a second side longer than the first side such that the second side provides a lower resistance path for a current flow.

公开(公告)号：US20160163450A1

公开(公告)日：2016-06-09

申请号：US15046302

申请日：2016-02-17

Applicant: QUALCOMM Incorporated

Inventor： David Francis BERDY ,  Chengjie ZUO ,  Daeik Daniel KIM ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Robert Paul MIKULKA ,  Jonghae KIM

IPC: H01F41/04

CPC classification number: H01F41/041 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/29 ,  H01F2017/004 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.

Abstract translation: 三维（3D）正交电感器对被嵌入并由衬底支撑，并且具有第一电感器，其具有卷绕第一绕组轴线的第一线圈和具有卷绕第二绕组轴线的第二线圈的第二电感器 。 第二卷绕轴线与第一卷绕轴线正交。 第二绕组轴线在第一绕组轴线处于衬底内的交点处。

公开(公告)号：US20150287677A1

公开(公告)日：2015-10-08

申请号：US14483944

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Jeffrey LAN ,  David Francis BERDY ,  Chengjie ZUO ,  Daeik Daniel KIM ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Niranjan Sunil MUDAKATTE ,  Robert Paul MIKULKA ,  Jonghae KIM

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L21/283

CPC classification number: H01L23/5227 ,  H01L21/283 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5329 ,  H01L27/01 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a substrate. The integrated circuit device also includes a first conductive stack including a back-end-of-line (BEOL) conductive layer at a first elevation with reference to the substrate. The integrated circuit device also includes a second conductive stack including the BEOL conductive layer at a second elevation with reference to the substrate. The second elevation differs from the first elevation.

Abstract translation: 集成电路器件包括衬底。 集成电路器件还包括第一导电叠层，其包括参考衬底的第一高度处的后端行（BEOL）导电层。 集成电路器件还包括第二导电叠层，其包括相对于衬底的第二高度处的BEOL导电层。 第二个高程与第一个高程不同。

公开(公告)号：US20150200245A1

公开(公告)日：2015-07-16

申请号：US14153917

申请日：2014-01-13

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Daeik Daniel KIM ,  Chengjie ZUO ,  Mario Francisco VELEZ ,  Jonghae KIM ,  David Francis BERDY

IPC: H01L49/02

CPC classification number: H01L28/88 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A lateral metal insulator metal (MIM) capacitor includes a first conductive plate, and a dielectric layer on a sidewall(s) and a first surface of the first conductive plate adjacent to the sidewall(s). The capacitor also includes a second conductive plate on a portion of the dielectric layer that is on the sidewall(s) and on a portion of the dielectric layer that covers a portion of the first surface of the first conductive plate. A sidewall capacitance is also greater than a surface capacitance of the capacitor.

Abstract translation: 横向金属绝缘体金属（MIM）电容器包括第一导电板和侧壁上的介电层以及邻近侧壁的第一导电板的第一表面。 所述电容器还包括位于所述侧壁上以及所述电介质层的覆盖所述第一导电板的所述第一表面的一部分的所述介电层的一部分上的第二导电板。 侧壁电容也大于电容器的表面电容。