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公开(公告)号：US20190035621A1
公开(公告)日：2019-01-31
申请号：US15659591
申请日：2017-07-25
发明人： Changhan Hobie YUN , Mario Francisco VELEZ , David Francis BERDY , Chengjie ZUO , Jonghae KIM , Niranjan Sunil MUDAKATTE , Xiaoju YU
摘要： To overcome the deficiencies of conventional rectangular circuit wafers, a glass substrate circuit wafer with an obtuse angle on the perimeter may be used. In one example, a glass substrate wafer may include a first circuit on a first portion of a glass substrate and a second circuit on a second portion of the glass substrate where the first portion has a first obtuse angle and the second portion has a second obtuse angle that is complementary to the first obtuse angle on the perimeter of the first portion to mate together to form an outer perimeter that comprises right angles.
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2.发明申请公开(公告)号：US20180054177A1
公开(公告)日：2018-02-22
申请号：US15240987
申请日：2016-08-18
发明人： Niranjan Sunil MUDAKATTE , David Francis BERDY , Changhan Hobie YUN , Chengjie ZUO , Shiqun GU , Mario Francisco VELEZ , Jonghae KIM
CPC分类号： H03H7/0115 , H01L28/10 , H01L28/40 , H03H1/0007 , H03H7/0138 , H03H7/46 , H03H2001/0078 , H03H2001/0085 , H05K1/0306 , H05K1/162 , H05K1/165 , H05K2201/09263 , H05K2201/09281
摘要： A passive device may include an inductor having interconnected trace segments. The passive device may also include parallel plate capacitors. Each of the plurality of parallel plate capacitors may have a dielectric layer between a pair of conductive plates. The parallel plate capacitors may not overlap more than one of the interconnected trace segments.
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公开(公告)号：US20180047687A1
公开(公告)日：2018-02-15
申请号：US15233902
申请日：2016-08-10
发明人： Daeik Daniel KIM , Jie FU , Manuel ALDRETE , Jonghae KIM , Changhan Hobie YUN , David Francis BERDY , Chengjie ZUO , Mario Francisco VELEZ
IPC分类号： H01L23/00 , H01L23/367 , H01L21/56 , H01L23/31
CPC分类号： H01L24/09 , H01L21/563 , H01L23/3157 , H01L23/3675 , H01L23/3677 , H01L23/481 , H01L23/49816 , H01L24/03 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/92 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/131 , H01L2224/14051 , H01L2224/14181 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/15321 , H01L2924/014 , H01L2924/00014
摘要： A semiconductor device according to some examples of the disclosure may include a package substrate, a semiconductor die coupled to one side of the package substrate with a first set of contacts on an active side of the semiconductor die and coupled to a plurality of solder prints with a second set of contacts on a back side of the semiconductor die. The semiconductor die may include a plurality of vias connecting the first set of contacts to the second set of contacts and configured to allow heat to be transferred from the active side of the die to the plurality of solder prints for a shorter heat dissipation path.
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公开(公告)号：US20170373025A1
公开(公告)日：2017-12-28
申请号：US15190158
申请日：2016-06-22
发明人： Daeik Daniel KIM , Changhan Hobie YUN , David Francis BERDY , Chengjie ZUO , Mario Francisco VELEZ , Jonghae KIM
IPC分类号： H01L23/64 , H01L23/522 , H01F41/04
CPC分类号： H01L23/645 , H01F41/041 , H01L23/49822 , H01L23/5227 , H01L23/5383 , H01L25/16 , H01L2224/16227 , H01L2924/19042 , H01L2924/19105 , H01L2924/30107
摘要： In conventional device packages, separate standalone inductors are provided and mounted on an interposer substrate along with a die. Separate inductors reduce integration density, decrease flexibility, increase footprint, and generally increase costs. To address such disadvantages, it is proposed to provide a part of an inductor in a substrate below a die. The proposed stacked substrate inductor may include a first inductor in a first substrate, a second inductor in a second a second substrate stacked on the first substrate, and an inductor interconnect coupling the first and second inductors. The core regions of the first and second inductors may overlap with each other at least partially. The proposed stacked substrate inductor may enhance integration density, increase flexibility, decrease footprint, and/or reduce costs.
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公开(公告)号：US20160254236A1
公开(公告)日：2016-09-01
申请号：US14633934
申请日：2015-02-27
发明人： Daeik Daniel KIM , Changhan Hobie YUN , Mario Francisco VELEZ , David Francis BERDY , Chengjie ZUO , Jonghae KIM , Matthew Michael NOWAK
IPC分类号： H01L23/60 , H01L25/00 , H01L23/00 , H01L25/065 , H01L23/31
CPC分类号： H01L23/60 , H01L23/3114 , H01L23/552 , H01L24/00 , H01L24/17 , H01L25/0655 , H01L25/50 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125
摘要： Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a multichip module or device, such as a multichip module or device with flip-chip (FC) bumps. Intra-module shielding between individual chips within the multichip module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a substrate or interposer to ensure reliable grounding.
摘要翻译： 接地屏蔽通过具有导电表面的导体屏蔽来实现，导电表面立即围绕多芯片模块或器件（例如具有倒装芯片（FC）凸块的多芯片模块或器件）中的单个芯片。 多芯片模块或设备内的单个芯片之间的模块间屏蔽通过由紧邻每个芯片的导体屏蔽表面提供的电磁或射频信号（RF）隔离来实现。 导体屏蔽件直接连接到基板或插入件的一个或多个接地导体部分，以确保可靠的接地。
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公开(公告)号：US20230299808A1
公开(公告)日：2023-09-21
申请号：US17655351
申请日：2022-03-17
发明人： David Francis BERDY , Jin CHO , Yu Steve ZHAO , Christian HOLENSTEIN , Ryan Scott Castro SPRING , Jose CABANILLAS , Euichan MOON
CPC分类号： H04B1/40 , H03H1/0007
摘要： In certain aspects, a system includes a first filter, a second filter, a dummy load, and a switching circuit coupled to the first filter, the second filter, and the dummy load, and coupled to a first antenna and a second antenna. In a first mode, the switching circuit couples the first filter and the second filter to the first antenna, and, in a second mode, the switching circuit couples the first filter and the third filter to the first antenna and couples the second filter to the second antenna. In certain aspects, the dummy load includes a third filter.
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公开(公告)号：US20180083589A1
公开(公告)日：2018-03-22
申请号：US15273596
申请日：2016-09-22
发明人： Changhan Hobie YUN , Chengjie ZUO , David Francis BERDY , Mario Francisco VELEZ , Niranjan Sunil MUDAKATTE , Jonghae KIM
CPC分类号： H03H7/0115 , H03H7/463 , H03H2001/0078 , H03H2001/0085 , H03H2007/013
摘要： The present disclosure provides circuits and methods for fabricating circuits. A circuit may include a first insulator, a second insulator, a first subset of circuit elements disposed on a bottom surface of the first insulator, a second subset of circuit elements disposed on a top surface of the second insulator, one or more conductive couplings disposed between the first subset of circuit elements and the second subset of circuit elements.
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公开(公告)号：US20180083588A1
公开(公告)日：2018-03-22
申请号：US15350969
申请日：2016-11-14
发明人： Changhan Hobie YUN , Shiqun GU , Je-Hsiung Jeffrey LAN , Jonghae KIM , Niranjan Sunil MUDAKATTE , David Francis BERDY , Mario Francisco VELEZ , Chengjie ZUO
CPC分类号： H03H1/00 , H01G4/005 , H01G4/012 , H01G4/1209 , H01G4/33 , H01G4/40 , H01L23/5223 , H01L28/60 , H03H7/46 , H03H7/463 , H03H2001/0014 , H03H2001/0021 , H04B1/0057 , H04B1/0458 , H04B1/18
摘要： A capacitor may include a first capacitor plate having a first length. The capacitor may also include an inorganic capacitor dielectric layer on sidewalls and a surface of the first capacitor plate and a second capacitor plate on the inorganic capacitor dielectric layer. The second capacitor plate may have a second length less than the first length of the first capacitor plate. The capacitor may also include a conductive contact landing directly on the first capacitor plate. The conductive contact may land directly on the first capacitor plate by extending through the inorganic capacitor dielectric layer and an organic interlayer dielectric supported by the inorganic capacitor dielectric layer.
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公开(公告)号：US20170338255A1
公开(公告)日：2017-11-23
申请号：US15161152
申请日：2016-05-20
发明人： Changhan Hobie YUN , Daeik Daniel KIM , Jonghae KIM , Mario Mario VELEZ , Chengjie ZUO , David Francis BERDY
CPC分类号： H01L27/13 , H01L21/84 , H01L23/49822 , H01L28/10 , H01L28/40 , H03H7/0115 , H03H2001/0085
摘要： The present disclosure provides integrated circuit apparatuses and methods for manufacturing integrated circuit apparatuses. An integrated circuit apparatus may include a first insulator, the first insulator being substantially planar and having a first top surface and a first bottom surface opposite the first top surface, a first conductor disposed on the first insulator, a second insulator, the second insulator being substantially planar and having a second top surface and a second bottom surface opposite the second top surface, a second conductor disposed on the second insulator, and a dielectric layer disposed between the first bottom conductor of the first insulator and the second top conductor of the second insulator.
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10.发明申请公开(公告)号：US20170140862A1
公开(公告)日：2017-05-18
申请号：US14941493
申请日：2015-11-13
发明人： Changhan Hobie YUN , David Francis BERDY , Daeik Daniel KIM , Chengjie ZUO , Jonghae KIM , Je-Hsiung Jeffrey LAN , Mario Francisco VELEZ , Niranjan Sunil MUDAKATTE
CPC分类号： H01F10/12 , H01F17/0013 , H01F27/2804 , H01F41/042 , H01F41/046 , H01F2017/0066 , H01F2027/2809
摘要： A thin film magnet (TFM) three-dimensional (3D) inductor structure may include a substrate with conductive vias extending through the substrate. The TFM 3D inductor structure may also include a magnetic thin film layer on at least sidewalls of the conductive vias and on a first side and an opposing second side of the substrate. The TFM 3D inductor structure may further include a first conductive trace directly on the magnetic thin film layer on the first side of the substrate and electrically coupling to at least one of the conductive vias. The TFM 3D inductor structure also includes a second conductive trace directly on the magnetic thin film layer on the second side of the substrate and coupled to at least one of the conductive vias.
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