公开(公告)号：US20150030112A1

公开(公告)日：2015-01-29

申请号：US14336572

申请日：2014-07-21

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley ,  Chulkyu Lee

IPC: H04L7/033

CPC classification number: H04L7/033 ,  G06F13/4295 ,  H04B3/02 ,  H04L7/0004 ,  H04L7/0337 ,  H04L25/0272 ,  H04L25/0292 ,  Y02D10/14 ,  Y02D10/151

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. A clock recovery circuit may be calibrated based on state transitions in a preamble transmitted on two or more connectors. A calibration method is described. The method includes detecting a plurality of transitions in a preamble of a multiphase signal and calibrating a delay element to provide a delay that matches a clocking period of the multiphase signal. Each transition may be detected by only one of a plurality of detectors. The delay element may be calibrated based on time intervals between detections of successive ones of the plurality of transitions.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 信息以N相极性编码符号发送。 时钟恢复电路可以基于在两个或更多个连接器上发送的前置码中的状态转换来校准。 描述校准方法。 该方法包括检测多相信号的前导码中的多个转换并校准延迟元件以提供与多相信号的计时周期匹配的延迟。 每个转换可以仅由多个检测器中的一个检测。 延迟元件可以基于多个转换中的连续检测之间的时间间隔进行校准。

公开(公告)号：US20140372644A1

公开(公告)日：2014-12-18

申请号：US14302365

申请日：2014-06-11

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC: G06F13/42 ,  G06F13/364

CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4295 ,  H04L7/0331

Abstract: System, methods and apparatus are described that include a serial bus, including a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. The bus has a first line and a second line, a first set of devices coupled to the bus and a second set of devices coupled to the bus. A method of operating the bus includes configuring the first set of devices to use the first line for data transmissions and use the second line for a first clock signal in a first mode of operation, and configuring the second set of devices to use both the first line and the second line for data transmissions while embedding a second clock signal within symbol transitions of the data transmissions in a second mode of operation.

Abstract translation: 描述了包括串行总线的系统，方法和装置，其包括用于互联集成电路（I2C）和/或相机控制接口（CCI）操作的串行总线。 总线具有第一线路和第二线路，耦合到总线的第一组设备和耦合到总线的第二组设备。 操作总线的方法包括配置第一组设备以使用第一行进行数据传输，并且在第一操作模式中使用第二行作为第一时钟信号，并且将第二组设备配置为使用第一组 线和用于数据传输的第二行，同时在第二操作模式中将第二时钟信号嵌入在数据传输的符号转换内。

公开(公告)号：US20140254712A1

公开(公告)日：2014-09-11

申请号：US14199064

申请日：2014-03-06

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu Lee ,  George Alan Wiley ,  Shoichiro Sengoku

IPC: H04B3/06

CPC classification number: H04B3/06 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. Each of the three terminals may be driven such that transistors are activated to couple a terminal to first and second voltage levels through a pair of impedances when the terminal would otherwise be undriven. The terminal is then pulled toward an intermediate voltage level while the terminal presents a desired impedance level to a transmission line.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 当传输线否则将被驱动时，传输线选择性地终止在N相极性编码的发射机中。 数据被映射到要在多根线上传输的符号序列。 符号序列被编码为三个信号。 可以驱动三个端子中的每一个，使得晶体管被激活以在端子否则将不被引导时通过一对阻抗将端子耦合到第一和第二电压电平。 然后将终端拉向中间电压电平，同时终端向传输线呈现期望的阻抗电平。

公开(公告)号：US20140153665A1

公开(公告)日：2014-06-05

申请号：US14090625

申请日：2013-11-26

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley ,  Glenn D. Raskin ,  Chulkyu Lee

IPC: H04L25/02

CPC classification number: H04L25/0272 ,  H04L5/20 ,  H04L25/0282 ,  H04L25/0294 ,  H04L25/0298 ,  H04L25/4917

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 信息以N相极性编码符号发送。 数据以多位符号编码，并且多位符号在多个连接器上传输。 可以通过将符号映射到多个连接器的状态序列来传输多比特符号，并且根据状态序列来驱动连接器。 状态序列的定时可以在连续状态之间的每个转换处在接收器处确定。 每个连接器的状态可以由在每个连接器上传输的多相信号的极性和旋转方向来定义。

公开(公告)号：US11463233B2

公开(公告)日：2022-10-04

申请号：US17307770

申请日：2021-05-04

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu Lee ,  George Alan Wiley

IPC: H04B14/04 ,  H04L7/00 ,  G06F13/42 ,  H04L12/40

Abstract: Methods, apparatus, and systems for communication over a C-PHY interface are disclosed. A transmitting device has a driver circuit configured to drive a three-wire bus in accordance with a symbol received at an input of the driver circuit, a pattern detector receives a sequence of symbols to be transmitted over the three-wire bus in a plurality of transmission symbol intervals, and a selection circuit responsive to a select signal provided by the pattern detector and configured to select between delayed and undelayed versions of a current symbol to drive the input of the driver circuit during a corresponding transmission symbol interval. The select signal may select the delayed version of the current symbol when a combination of the current symbol with an immediately preceding symbol cause the pattern detector to indicate a pattern match.

公开(公告)号：US20220123987A1

公开(公告)日：2022-04-21

申请号：US17076190

申请日：2020-10-21

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  George Alan Wiley ,  Radu Pitigoi-Aron

IPC: H04L27/36 ,  H04L1/00 ,  H04L25/49

Abstract: Pulse amplitude modulation (PAM) encoding for a communication bus is disclosed. In particular, various two-wire communication buses may encode bits using three-level PAM (PAM-3) or five-level PAM (PAM-5) to increase bit transmission without requiring increases to clock frequencies or adding additional pins. Avoiding increases in clock frequencies helps reduce the risk of electromagnetic interference (EMI), and avoiding use of extra pins avoids cost increases for integrated circuits (ICs).

公开(公告)号：US20210326290A1

公开(公告)日：2021-10-21

申请号：US17363407

申请日：2021-06-30

Applicant: QUALCOMM Incorporated

Inventor： Richard Dominic Wietfeldt ,  Maxime Leclercq ,  George Alan Wiley

IPC: G06F13/40 ,  G06F13/38 ,  H04L12/26

Abstract: Unified systems and methods for interchip and intrachip node communication are disclosed. In one aspect, a single unified low-speed bus is provided that connects each of the chips within a computing device. The chips couple to the bus through a physical layer interface and associated gateway. The gateway includes memory that stores a status table summarizing statuses for every node in the interface fabric. As nodes experience state changes, the nodes provide updates to associated local gateways. The local gateways then message, using a scout message, remote gateways with information relating to the state changes. When a first node is preparing a signal to a second node, the first node checks the status table at the associated local gateway to determine a current status for the second node. Based on the status of the second node, the first node may send the message or take other appropriate action.

公开(公告)号：US11108604B2

公开(公告)日：2021-08-31

申请号：US16984896

申请日：2020-08-04

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu Lee ,  Dhaval Sejpal ,  George Alan Wiley

IPC: H04B1/00 ,  H04L27/20 ,  H04L27/233 ,  H04L27/227

Abstract: Certain disclosed methods, apparatus, and systems enable improved communication on a multiphase communication link through improved encoding techniques and protocol. A data communication apparatus has a plurality of line drivers configured to couple the apparatus to a 3-wire link, and a data encoder configured to encode at least 3 bits of binary data in each transition between two symbols that are consecutively transmitted by the plurality of line drivers over the 3-wire link such that each pair of consecutively-transmitted symbols comprises two different symbols. Each symbol defines signaling states of the 3-wire link during an associated symbol transmission interval such that each wire of the 3-wire link is in a different signaling state from the other wires of the 3-wire link during the associated symbol transmission interval. Data may be encoded using a combination of 3-phase and pulse amplitude modulation.

公开(公告)号：US10355894B2

公开(公告)日：2019-07-16

申请号：US16128348

申请日：2018-09-11

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley

IPC: H04B3/00 ,  H04L27/20 ,  H04L25/02 ,  H04L25/49

Abstract: Systems, methods and apparatus are described that facilitate transmission of data between two devices within an electronic apparatus. An apparatus has a bus interface, a 3-phase encoder, and a processing circuit that can configure the 3-phase encoder for a first mode of operation in which data is encoded in a sequence of two-bit symbols, transmit a first three-phase signal representative of the sequence of two-bit symbols on each of the three wires. The processing circuit may be configured to configure the 3-phase encoder for a second mode of operation in which data is encoded in a sequence of three-bit symbols. Three-phase signal representative of the sequence of two-bit symbols or sequence of three-bit symbols on each of three wires, where a three-phase signal is in a different phase on each wire when transmitted, and a transition in signaling state occurs between transmission of each pair of symbols.

公开(公告)号：US10027504B2

公开(公告)日：2018-07-17

申请号：US15299260

申请日：2016-10-20

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley

IPC: H04L12/40 ,  G06F13/42

Abstract: System, methods and apparatus are described that support multimode operation of a data communication interface. A method includes receiving a first code word transmitted while a physical interface of the device is configured to operate in a low-power mode of operation, reconfiguring the physical interface in response to the first code word such that it operates in a high-speed mode, transmitting data while the physical interface operates in the high-speed mode of operation, receiving a second code word transmitted while the physical interface operated in the high-speed mode of operation, and reconfiguring the physical interface in response to the second code word, such that it operates in the low-power mode of operation. The first code word, the second code word, and the data may be transmitted in signals bound by a common voltage range. In one example, the voltage range is less than 600 millivolts.