公开(公告)号：US10325979B1

公开(公告)日：2019-06-18

申请号：US15860005

申请日：2018-01-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Jun Chen ,  Yangyang Sun ,  Stanley Seungchul Song ,  Giridhar Nallapati

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/91 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283

Abstract: Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a substrate, a first group of metal layers including a plurality of first fingers over the substrate, wherein the first fingers are formed without a via. The integrated circuit may further include a second group of metal layers including a plurality of second fingers over the first group of metal layers, wherein the second fingers are formed with vias, and wherein the first and the second group of metal layers are formed by a processing technology node of 7 nm or below.

公开(公告)号：US09287347B2

公开(公告)日：2016-03-15

申请号：US13765015

申请日：2013-02-12

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  P R Chidambaram ,  Giridhar Nallapati ,  Choh fei Yeap

IPC: H01L29/49 ,  H01L49/02 ,  H01L23/64 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L23/642 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal-insulator-metal (MIM) capacitor reduces a number of masks and processing steps compared to conventional techniques. A first conductive layer of a MIM capacitor is deposited on a semiconductor chip and patterned using a MIM conductive layer mask. A conductive redistribution layer (RDL) is patterned over the MIM dielectric layer. The conductive redistribution layer includes two RDL nodes that overlap the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

Abstract translation: 与常规技术相比，金属 - 绝缘体 - 金属（MIM）电容器减少了许多掩模和处理步骤。 MIM电容器的第一导电层沉积在半导体芯片上并使用MIM导电层掩模进行图案化。 导电再分配层（RDL）在MIM介电层上图案化。 导电再分配层包括与MIM电容器的第一导电层重叠的两个RDL节点。 导电通孔或凸块延伸穿过MIM介电层，并将RDL节点之一耦合到MIM电容器的第一导电层。

公开(公告)号：US09245971B2

公开(公告)日：2016-01-26

申请号：US14040366

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  P R Chidambaram ,  John Jianhong Zhu ,  Jihong Choi ,  Da Yang ,  Ravi Mahendra Todi ,  Giridhar Nallapati ,  Chock Hing Gan ,  Ming Cai ,  Samit Sengupta

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/8238

CPC classification number: H01L29/66431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/778 ,  H01L29/7834

Abstract: In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel.

Abstract translation: 在特定实施例中，半导体器件包括源极区和漏极区之间的高迁移率沟道。 高迁移率通道基本上延伸了一个门的长度。 半导体器件还包括从源极区域或漏极区域向高迁移率通道延伸的掺杂区域。 衬底的一部分位于掺杂区域和高迁移率通道之间。

公开(公告)号：US20140225224A1

公开(公告)日：2014-08-14

申请号：US13765015

申请日：2013-02-12

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  PR Chidambaram ,  Giridhar Nallapati ,  Choh fei Yeap

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L23/642 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal-insulator-metal (MIM) capacitor reduces a number of masks and processing steps compared to conventional techniques. A first conductive layer of a MIM capacitor is deposited on a semiconductor chip and patterned using a MIM conductive layer mask. A conductive redistribution layer (RDL) is patterned over the MIM dielectric layer. The conductive redistribution layer includes two RDL nodes that overlap the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

Abstract translation: 与常规技术相比，金属 - 绝缘体 - 金属（MIM）电容器减少了许多掩模和处理步骤。 MIM电容器的第一导电层沉积在半导体芯片上并使用MIM导电层掩模进行图案化。 导电再分配层（RDL）在MIM介电层上图案化。 导电再分配层包括与MIM电容器的第一导电层重叠的两个RDL节点。 导电通孔或凸块延伸穿过MIM介电层，并将RDL节点之一耦合到MIM电容器的第一导电层。

公开(公告)号：US08782576B1

公开(公告)日：2014-07-15

申请号：US13975781

申请日：2013-08-26

Applicant: QUALCOMM Incorporated

Inventor： Benjamin John Bowers ,  James W. Hayward ,  Charanya Gopal ,  Gregory Christopher Burda ,  Robert J. Bucki ,  Chock H. Gan ,  Giridhar Nallapati ,  Matthew D. Youngblood ,  William R. Flederbach

IPC: G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/22 ,  H01L27/092 ,  H01L27/11521 ,  H01L27/11803 ,  H01L27/11807 ,  H01L29/66825 ,  Y02P90/265

Abstract: A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.

Abstract translation: 用于设计集成电路的单元库，该库包括连续扩散兼容（CDC）单元。 CDC单元包括电连接到电源轨的p掺杂扩散区，并且连接于CDC单元的左边缘到右边缘; 第一多晶硅栅极，设置在p掺杂扩散区上方并电连接到p掺杂扩散区; 电连接到接地导轨并从左边缘到右边缘连续的n掺杂扩散区域; 第二多晶硅栅极，其设置在所述n掺杂扩散区域上方并电连接到所述n掺杂扩散区域; 设置在p掺杂和n掺杂扩散区上并靠近左边缘的左浮动多晶硅栅极; 以及设置在p掺杂和n掺杂扩散区域上并且靠近右边缘的右浮动多晶硅栅极。

公开(公告)号：US20140124868A1

公开(公告)日：2014-05-08

申请号：US13671114

申请日：2012-11-07

Applicant: QUALCOMM INCORPORATED

Inventor： Pratyush Kamal ,  Esin Terzioglu ,  Foua Vang ,  Prayag Bhanubhai Patel ,  Giridhar Nallapati ,  Animesh Datta

IPC: H01L27/092 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/66545 ,  H01L2027/11831

Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.

Abstract translation: 半导体标准单元包括N型扩散区和P型扩散区，两者均延伸穿过电池并且还在电池外部。 电池还包括在每个扩散区域上方的导电栅极以产生半导体器件。 一对虚拟栅极也在N型扩散区域和P型扩散区域之上，形成一对虚设装置。 一对虚拟门设置在电池的相对边缘。 电池还包括第一导线，其被配置为将虚设装置耦合到用于禁用虚设装置的电力。