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    Mask-programmed read only memory with enhanced security
    1.
    发明授权
    Mask-programmed read only memory with enhanced security 有权
    面板编程只读存储器，增强安全性

    公开(公告)号：US09484110B2

    公开(公告)日：2016-11-01

    申请号：US13953511

    申请日：2013-07-29

    Applicant: QUALCOMM Incorporated

    Inventor： Sei Seung Yoon ,  Chulmin Jung ,  Esin Terzioglu ,  Steven Mark Millendorf

    IPC: G11C17/12 ,  G11C7/24

    CPC classification number: G11C17/12 ,  G11C7/24

    Abstract: A mask-programmed read-only memory (MROM) has a plurality of column line pairs, each having a bit line and a complement bit line. The MROM includes a plurality of memory cells corresponding to a plurality of intersections between the column line pairs and a plurality of word lines. Each memory cell includes a high Vt transistor and a low Vt transistor.

    Abstract translation: 掩模编程的只读存储器（MROM）具有多个列线对，每一列具有位线和补码位线。 MROM包括与列线对和多个字线之间的多个交点相对应的多个存储单元。 每个存储单元包括高Vt晶体管和低Vt晶体管。

    STATIC NAND CELL FOR TERNARY CONTENT ADDRESSABLE MEMORY (TCAM)
    3.
    发明申请
    STATIC NAND CELL FOR TERNARY CONTENT ADDRESSABLE MEMORY (TCAM) 有权
    用于内部可寻址存储器（TCAM）的静态NAND单元

    公开(公告)号：US20150085554A1

    公开(公告)日：2015-03-26

    申请号：US14503861

    申请日：2014-10-01

    Applicant: QUALCOMM Incorporated

    Inventor： Esin Terzioglu ,  Nishith Desai ,  Rakesh Vattikonda ,  ChangHo Jung ,  Sei Seung Yoon

    IPC: G11C15/04

    CPC classification number: G11C15/04 ,  G11C15/00 ,  G11C15/043 ,  G11C15/046

    Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.

    Abstract translation: 静态三元内容可寻址存储器（TCAM）包括密钥单元和耦合到中间匹配行的掩码单元。 关键单元耦合到第一下拉晶体管和第一上拉晶体管。 掩模单元耦合到第二下拉晶体管和第二上拉晶体管。 第一下拉晶体管和第二下拉晶体管并联连接，第一上拉晶体管和第二上拉晶体管串联连接。 匹配线输出还耦合到第一下拉晶体管和第二下拉晶体管，并且还耦合到第一上拉晶体管和第二上拉晶体管。

    N-WELL SWITCHING CIRCUIT
    4.
    发明申请
    N-WELL SWITCHING CIRCUIT 有权
    N-Well切换电路

    公开(公告)号：US20140369152A1

    公开(公告)日：2014-12-18

    申请号：US14472953

    申请日：2014-08-29

    Applicant: QUALCOMM Incorporated

    Inventor： Esin Terzioglu ,  Gregory Ameriada Uvieghara ,  Sei Seung Yoon ,  Balachander Ganesan ,  Anil Chowdary Kota

    IPC: H03K17/22 ,  H03K17/687 ,  G11C8/08

    CPC classification number: H03K17/223 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C13/0069 ,  G11C17/18 ,  H03K17/08104 ,  H03K17/6872 ,  H03K19/00315 ,  H03K2217/0018 ,  H03K2217/0063 ,  H03K2217/0072

    Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

    Abstract translation: 公开了一种双模式PMOS晶体管，其具有第一工作模式，其中用于双模式PMOS晶体管的开关n阱被偏置到高电压。 双模式PMOS晶体管具有第二工作模式，其中开关n阱被偏置成低于高电压的低电压。 双模式PMOS晶体管的尺寸和栅极氧化物厚度各自具有不能适应与高电压的永久连接的幅度。 n阱电压开关电路偏置开关n阱，以防止电压损坏双模PMOS晶体管，尽管其尺寸相对较小，栅极氧化物厚度较薄。

    GLOBAL RESET WITH REPLICA FOR PULSE LATCH PRE-DECODERS
    7.
    发明申请
    GLOBAL RESET WITH REPLICA FOR PULSE LATCH PRE-DECODERS 有权
    全面复位与脉冲锁定前缀解码器

    公开(公告)号：US20130223178A1

    公开(公告)日：2013-08-29

    申请号：US13663042

    申请日：2012-10-29

    Applicant: QUALCOMM Incorporated

    Inventor： Esin Terzioglu ,  Changho Jung ,  Shahzad Nazar ,  Balachander Ganesan ,  Alex Dongkyu Park

    IPC: G11C8/10

    CPC classification number: G11C8/10

    Abstract: A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal to reset the pulse latch circuit, providing a combined signal of the pre-decoded memory address output and the reset signal, feeding the combined signal into a low voltage threshold device to manipulate resetting the pulse latch circuit, wherein generating a reset signal comprises generating a reset signal from a matched circuit that is configured to mimic the function of the latch circuit to be reset and wherein generating a reset signal comprises configuring the matched circuit to accommodate a worst case hold pulse delay to allow for resetting the pulse latch before a new clock cycle performs the resetting and having the matched circuit provide the reset signal and a pre-decoded memory address output in the same voltage domain.

    Abstract translation: 一种用于存储器中基于脉冲锁存器的预解码器的全局复位产生方法，包括产生用于脉冲锁存电路的预解码存储器地址输出，产生复位信号以复位脉冲锁存电路，提供预处理器的组合信号， 解码的存储器地址输出和复位信号，将组合的信号馈送到低电压阈值器件以操纵复位脉冲锁存电路，其中产生复位信号包括产生来自匹配电路的复位信号，该匹配电路被配置为模拟 锁存电路被复位并且其中产生复位信号包括配置匹配电路以适应最坏情况保持脉冲延迟，以允许在新的时钟周期执行复位之前复位脉冲锁存器并使匹配电路提供复位信号和 在同一电压域内预编译的存储器地址输出。

    SOC design with critical technology pitch alignment
    8.
    发明授权
    SOC design with critical technology pitch alignment 有权
    SOC设计与关键技术音调对齐

    公开(公告)号：US09331016B2

    公开(公告)日：2016-05-03

    申请号：US14338229

    申请日：2014-07-22

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangdong Chen ,  Ohsang Kwon ,  Esin Terzioglu ,  Hadi Bunnalim

    IPC: H01L29/40 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528

    CPC classification number: H01L23/5226 ,  H01L23/498 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects. The vias have a minimum pitch v. The values m, g, and v are such that g2+m2≧v2 and an LCM of g and m is less than 20 g. The SOC apparatus may further include a second plurality of metal interconnects with a minimum pitch of m2, where m2>m and the LCM of g, m, and m2 is less than 20 g.

    Abstract translation: SOC装置包括具有最小间距g的多个栅极互连，具有最小间距m的多个金属互连以及互连栅极互连和金属互连的多个通孔。 通孔具有最小间距v。值m，g和v使得g2 +m2≥2v，g和m的LCM小于20g。 SOC装置还可以包括具有最小间距m2的第二多个金属互连，其中m2> m且g，m和m2的LCM小于20g。

    MASK-PROGRAMMED READ ONLY MEMORY WITH ENHANCED SECURITY
    10.
    发明申请
    MASK-PROGRAMMED READ ONLY MEMORY WITH ENHANCED SECURITY 有权
    屏蔽编程只读具有增强安全性的存储器

    公开(公告)号：US20150029778A1

    公开(公告)日：2015-01-29

    申请号：US13953511

    申请日：2013-07-29

    Applicant: QUALCOMM Incorporated

    Inventor： Sei Seung Yoon ,  Chulmin Jung ,  Esin Terzioglu ,  Steven Millendorf

    IPC: G11C17/12

    CPC classification number: G11C17/12 ,  G11C7/24

    Abstract: A mask-programmed read-only memory (MROM) has a plurality of column line pairs, each having a bit line and a complement bit line. The MROM includes a plurality of memory cells corresponding to a plurality of intersections between the column line pairs and a plurality of word liens. Each memory cell includes a high Vt transistor and a low Vt transistor.

    Abstract translation: 掩模编程的只读存储器（MROM）具有多个列线对，每一列具有位线和补码位线。 MROM包括与列线对和多个字留置权之间的多个交点相对应的多个存储单元。 每个存储单元包括高Vt晶体管和低Vt晶体管。

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