公开(公告)号：US20240243056A1

公开(公告)日：2024-07-18

申请号：US18155398

申请日：2023-01-17

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  Manuel Aldrete ,  Wei Wang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/49894 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/105 ,  H01L24/16 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094

Abstract: Integrated circuit (IC) packages employing a re-distribution layer (RDL) substrate(s) with photosensitive non-polymer dielectric material layers for increased package rigidity, and related fabrication methods. To reduce or minimize warpage of an IC package employing a RDL substrate, the RDLs of the RDL substrate are photosensitive non-polymer dielectric material layers. The photosensitive non-polymer dielectric material layers can exhibit increased rigidity as a result of being hardened when exposed to light and cured during fabrication of the RDL substrate. The photosensitive non-polymer dielectric material layers can also exhibit increased rigidity as a result of being an inorganic polymer (e.g., SiOx, SiN material) that has a higher material modulus for increased stiffness and/or a lower coefficient of thermal expansion (CTE) for reduced thermal contraction and expansion, as opposed to for example, an organic polymer material (e.g., Polyimide) which has less stiffness and a higher CTE.

公开(公告)号：US11557557B2

公开(公告)日：2023-01-17

申请号：US16917295

申请日：2020-06-30

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  Dongming He ,  Lily Zhao

IPC: H01L23/00

Abstract: Disclosed is a flip-chip device. The flip-chip device includes a die having a plurality of under bump metallizations (UBMs); and a package substrate having a plurality of bond pads. The plurality of UBMs include a first set of UBMs having a first size and a first minimum pitch and a second set of UBMs having a second size and a second minimum pitch. The first set of UBMs and the second set of UBMs are each electrically coupled to the package substrate by a bond-on-pad connection.

公开(公告)号：US20240387429A1

公开(公告)日：2024-11-21

申请号：US18318691

申请日：2023-05-16

Applicant: QUALCOMM Incorporated

Inventor： Yujen Chen ,  Yangyang Sun ,  Wei Wang

IPC: H01L23/00

Abstract: Underfill and bump interconnects in a circuit package expand at different rates during a thermal reflow process, causing stress at one end of a bump interconnect that couples to a metal pad. A bump interconnect having multiple isolated areas of contact between a conductive pillar and the metal pad, rather than a single larger continuous contact area, distributes the concentration of stresses to reduce the peak stress, which reduces the chances of damage due to stress occurring between the metal pad and the conductive pillar or in a dielectric layer adjacent to the metal pad. In some examples, before formation of the conductive pillar, a passivation layer is disposed in a pattern on the metal pad with openings in which a plurality of surfaces of the second end of the conductive pillar contact the metal pad.

公开(公告)号：US12113038B2

公开(公告)日：2024-10-08

申请号：US17027316

申请日：2020-09-21

Applicant: QUALCOMM Incorporated

Inventor： Dongming He ,  Hung-Yuan Hsu ,  Yangyang Sun ,  Wei Hu ,  Wei Wang ,  Lily Zhao

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/13027 ,  H01L2924/35

Abstract: A thermal compression flip chip (TCFC) bump may be used for high performance products that benefit from a fine pitch. In one example, a new TCFC bump structure adds a metal pad underneath the TCFC copper pillar bump to cover the exposed aluminum bump pad. This new structure prevents the pad from corroding and reduces mechanical stress to the pad and underlying silicon dielectric layers enabling better quality and reliability and further bump size reduction. For example, a flip chip connection may include a substrate; a metal pad on a contact side of the substrate and a first passivation layer on the contact side of the substrate to protect the metal pad from corrosion.

公开(公告)号：US11948909B2

公开(公告)日：2024-04-02

申请号：US17574360

申请日：2022-01-12

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  Dongming He ,  Lily Zhao

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/73 ,  H01L24/26 ,  H01L24/32 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/33 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13082 ,  H01L2224/16148 ,  H01L2224/26125 ,  H01L2224/2919 ,  H01L2224/301 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06565

Abstract: A package that includes a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.

公开(公告)号：US10325979B1

公开(公告)日：2019-06-18

申请号：US15860005

申请日：2018-01-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Jun Chen ,  Yangyang Sun ,  Stanley Seungchul Song ,  Giridhar Nallapati

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/91 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283

Abstract: Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a substrate, a first group of metal layers including a plurality of first fingers over the substrate, wherein the first fingers are formed without a via. The integrated circuit may further include a second group of metal layers including a plurality of second fingers over the first group of metal layers, wherein the second fingers are formed with vias, and wherein the first and the second group of metal layers are formed by a processing technology node of 7 nm or below.

公开(公告)号：US20140124877A1

公开(公告)日：2014-05-08

申请号：US13764261

申请日：2013-02-11

Applicant: QUALCOMM INCORPORATED

Inventor： Yangyang Sun ,  Lily Zhao ,  Michael Han

IPC: H01L29/43 ,  H01L29/84 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L29/43 ,  B81B2207/093 ,  B81C1/00269 ,  B81C2203/019 ,  H01L21/768 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L29/84 ,  H01L2224/02166 ,  H01L2224/03019 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/10126 ,  H01L2224/11019 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/1183 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13138 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13163 ,  H01L2224/13565 ,  H01L2224/13687 ,  H01L2224/13688 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/05442 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/01034 ,  H01L2924/0109 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A conductive interconnect includes an inorganic collar. The conductive interconnect includes a conductive support layer. The conductive interconnect also includes a conductive material on the conductive support layer. The conductive interconnect further includes an inorganic collar partially surrounding the conductive material. The inorganic collar is also disposed on sidewalls of the conductive support layer.

Abstract translation: 导电互连包括无机套环。 导电互连包括导电支撑层。 导电互连件还包括在导电支撑层上的导电材料。 导电互连还包括部分地围绕导电材料的无机套管。 无机套环也设置在导电支撑层的侧壁上。

公开(公告)号：US20230299048A1

公开(公告)日：2023-09-21

申请号：US17655394

申请日：2022-03-18

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  Stanley Seungchul Song ,  Lily Zhao

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06586 ,  H01L2225/06541 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L24/14

Abstract: A three-dimensional (3D) integrated circuit (IC) (3DIC) package with a bottom die layer employing an interposer substrate, and related fabrication methods. To facilitate the ability to fabricate the 3DIC package using a top die-to-bottom wafer process, a bottom die layer of the 3DIC package includes an interposer substrate. This interposer substrate provides support for a bottom die(s) of the 3DIC package. The interposer substrate is extended in length to be longer in length than the top die. The interposer substrate provides additional die area in the bottom die layer in which a larger length, top die can be bonded. In this manner, the bottom die layer, with its extended interposer substrate, can be formed in a bottom wafer in which the top die can be bonded in a top die-to-bottom wafer fabrication process.

公开(公告)号：US11676922B2

公开(公告)日：2023-06-13

申请号：US16665883

申请日：2019-10-28

Applicant: QUALCOMM Incorporated

Inventor： Li-Sheng Weng ,  Yue Li ,  Yangyang Sun

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/10122 ,  H01L2224/1182 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/14133 ,  H01L2924/3025

Abstract: An integrated device that includes a substrate, an interconnect portion and an interconnect structure. The interconnect portion is located over the substrate. The interconnect portion includes a plurality of interconnects and at least one dielectric layer. The interconnect structure is located over the interconnect portion. The interconnect structure includes an inner interconnect, a dielectric layer coupled to the inner interconnect, and an outer conductive layer coupled to the dielectric layer. The outer conductive layer is configured to operate as a shield for the inner interconnect.

公开(公告)号：US11417622B2

公开(公告)日：2022-08-16

申请号：US17071432

申请日：2020-10-15

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  John Holmes ,  Xuefeng Zhang ,  Dongming He

IPC: H01L23/00

Abstract: Disclosed are devices, fabrication methods and design rules for flip-chip devices. Aspects include an apparatus including a flip-chip device. The flip-chip device including a die having a plurality of under bump metallizations (UBMs). A package substrate having a plurality of bond pads is also included. A plurality of solder joints coupling the die to the package substrate. The plurality of solder joints are formed from a plurality of solder bumps plated on the plurality of UBMs, where the plurality of solder bumps are directly connected to the plurality of bond pads.