公开(公告)号：US20240321631A1

公开(公告)日：2024-09-26

申请号：US18190024

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Junjing BAO ,  Bin YANG ,  Biswa Ranjan PANDA ,  Ramesh MANCHANA

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53257 ,  H01L23/5329

Abstract: An integrated circuit (IC) includes back-end-of-line (BEOL) interconnects in a first intermetal dielectric (IMD) layer on a substrate. The IC also includes second BEOL interconnects on the first IMD layer, coupled to the first BEOL interconnects through first BEOL vias in the first IMD layer. The IC further includes a second IMD layer on the second BEOL interconnects to seal airgaps between the plurality of second BEOL interconnects. The IC also includes etch stop spacers on portions of sidewalls of the second BEOL interconnects to separate the portions of the sidewalls from the second IMD layer. The IC further includes third BEOL interconnects on the second IMD layer and coupled to one or more of the second BEOL interconnects through second BEOL vias in the second IMD layer.

公开(公告)号：US20240266217A1

公开(公告)日：2024-08-08

申请号：US18166403

申请日：2023-02-08

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Haining YANG ,  Hyunwoo PARK ,  Kwanyong LIM ,  Ming-Huei LIN

IPC: H01L21/768 ,  H01L21/321 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/3212 ,  H01L29/66545 ,  H01L29/6656

Abstract: Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a gate structure disposed on a substrate, a gate spacer adjacent to the gate structure, a source/drain structure adjacent to the gate spacer, a first dielectric layer disposed on the substrate and the source/drain structure, an etch stop spacer over the first dielectric layer and adjacent to the gate spacer, and an etch stop layer over the gate structure, the gate spacer, and the etch stop spacer. The semiconductor structure further includes a source/drain contact extending through the etch stop layer and the first dielectric layer and in contact with the source/drain structure, a sidewall of the source/drain contact adjoining a sidewall of the etch stop layer and a sidewall of the etch stop spacer.

公开(公告)号：US20240204109A1

公开(公告)日：2024-06-20

申请号：US18068992

申请日：2022-12-20

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Junjing BAO ,  Giridhar NALLAPATI

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/78696 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/0673

Abstract: Disclosed are complementary field effect transistors (CFETs) with balanced n and p drive current, and methods for making the same. In an aspect, a CFET structure comprises an nFET with horizontal p-doped nanosheet channels arranged in a first vertical stack, each horizontal p-doped nanosheet channel having a width W1, and connecting a first source contact to a first drain contact through a first gate-all-around (GAA) region having a length L1. The CFET structure further comprises a pFET with horizontal n-doped nanosheet channels arranged in a second vertical stack disposed on the first vertical stack, each horizontal n-doped nanosheet channel having a width W2, and connecting a second source contact to a second drain contact through a second GAA region having a length L2, wherein W2/L2 is not equal to W1/L1.

公开(公告)号：US20240096698A1

公开(公告)日：2024-03-21

申请号：US17933683

申请日：2022-09-20

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Chih-Sung YANG ,  Haining YANG

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/76879 ,  H01L27/10855

Abstract: In an aspect, a transistor comprises a gate structure having a metal gate, a dielectric layer at least partially surrounding the metal gate, a metal cap over a portion of the metal gate that is not surrounded by the dielectric layer, and a gate contact comprising tungsten in direct contact with the metal cap. In another aspect, a transistor comprises source, drain, and channel regions, a gate structure comprising a metal gate between gate spacers above the channel region, and a source or drain (S/D) contact structure. The S/D contact structure comprises an S/D barrier layer above at least a portion of the source or drain region and in direct contact with a gate spacer, and an S/D contact, comprising a first portion above the S/D barrier layer; and a second portion comprising tungsten, above the first portion.

公开(公告)号：US20220352347A1

公开(公告)日：2022-11-03

申请号：US17245695

申请日：2021-04-30

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Haining YANG ,  Youseok SUH

IPC: H01L29/66 ,  H01L23/535 ,  H01L29/417 ,  H01L21/02 ,  H01L21/768

Abstract: In some aspects, a semiconductor die includes an insulation layer disposed on a substrate, a gate spacer disposed in the insulation layer, a gate disposed between the gate spacer, a first dielectric gate layer disposed on the gate between the gate spacer, a second dielectric gate layer disposed on the first dielectric gate layer between the gate spacer, a gate contact coupled to the gate and in contact with the first dielectric gate layer and the second dielectric gate layer, and a source/drain contact that has a single inner spacer.

公开(公告)号：US20220336608A1

公开(公告)日：2022-10-20

申请号：US17231284

申请日：2021-04-15

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG ,  Junjing BAO

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/40 ,  H01L21/8238

Abstract: In an aspect, a semiconductor device includes a gate. The gate includes a first portion that is located on one end of the gate, a second portion that is located on an opposite end of the gate from the first portion, and a third portion that is located in-between the first portion and the second portion. A first cap located on top of the first portion. A second cap located on top of the second portion. The third portion is capless. A gate contact is located on top of the third portion.

公开(公告)号：US20210343830A1

公开(公告)日：2021-11-04

申请号：US16866316

申请日：2020-05-04

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Ye LU ,  Junjing BAO

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/768

Abstract: Certain aspects of the present disclosure generally relate to a metal-oxide-metal (MOM) capacitor formed from a subtractive back-end-of-line (BEOL) scheme. One example method of fabricating a semiconductor device generally includes forming an active layer and forming a capacitive element above the active layer with a back-end-of-line subtractive process for conductive materials.

公开(公告)号：US20210305155A1

公开(公告)日：2021-09-30

申请号：US16834618

申请日：2020-03-30

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Giridhar NALLAPATI ,  Peijie FENG

IPC: H01L23/522 ,  H01L21/768

Abstract: An integrated circuit (IC) is described. The IC includes a substrate having an active device having an active region. The IC also includes a middle-of-line (MOL) interconnect layer having a contact merge (CM) layer on a trench contact coupled to the active region of the active device. The IC further includes back-end-of-line (BEOL) interconnect layers on the MOL interconnect layer. The IC also includes a metal resistor in a via zero interconnect layer between a first BEOL interconnect and the MOL interconnect layer. The metal resistor is coupled to the active region through a first via zero on the CM layer, a second via zero on the metal resistor, and the first BEOL interconnect on the first via zero and the second via zero.

公开(公告)号：US20200234999A1

公开(公告)日：2020-07-23

申请号：US16250098

申请日：2019-01-17

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Junjing BAO ,  Peijie FENG ,  Chenjie TANG

IPC: H01L21/764 ,  H01L27/092 ,  H01L21/8238

Abstract: Certain aspects of the present disclosure provide a transistor device, such as a fin field-effect transistor (finFET) device, and techniques for fabrication thereof. One example transistor device generally includes one or more semiconductor channel regions and a metal region disposed above the one or more semiconductor channel regions. The metal region has one or more gaps (e.g., air gaps) disposed therein.

公开(公告)号：US20190385947A1

公开(公告)日：2019-12-19

申请号：US16007921

申请日：2018-06-13

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Junjing BAO ,  Bin YANG ,  Gengming TAO

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/528 ,  H01L23/66

Abstract: A capacitor includes a first set of conductive fingers having a first conductive pitch at a first interconnect layer and arranged in a first unidirectional routing. The capacitor further includes a second set of conductive fingers having a second conductive pitch at a second interconnect layer and arranged in a second unidirectional routing that is orthogonal to the first unidirectional routing. The first conductive pitch is different from the second conductive pitch. A first set of through finger vias electrically couples the first set of conductive fingers of the first interconnect layer to the second set of conductive fingers of the second interconnect layer. A third set of conductive fingers at a third conductive layer are parallel to, but offset from, the first set of conductive fingers. A second set of through finger vias electrically couples the third set of conductive fingers to the second set of conductive fingers.