公开(公告)号：US11152272B2

公开(公告)日：2021-10-19

申请号：US16682554

申请日：2019-11-13

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Jonghae Kim ,  Ranadeep Dutta

IPC: H01L23/15 ,  H01L21/02 ,  H01L21/8238

Abstract: Certain aspects provide a three-dimensional integrated circuit (3DIC) and techniques for fabricating a 3DIC. For example, certain aspects provide a semiconductor device that generally includes one or more first integrated circuits (ICs), a first plurality of pads coupled to components of the one or more first ICs, one or more second ICs, forming glass (FG) material disposed adjacent to the one or more second ICs, and a second plurality of pads, wherein at least one of the second plurality of pads is coupled to components of the one or more second ICs, and wherein at least a portion of the first plurality of pads is bonded to at least a portion of the second plurality of pads.

公开(公告)号：US10950721B2

公开(公告)日：2021-03-16

申请号：US16401189

申请日：2019-05-02

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: Certain aspects of the present disclosure generally relate to a transistor having a self-aligned drift region and asymmetric spacers. One example transistor generally includes a channel region; a gate region disposed above the channel region; a first implant region; a second implant region having a same doping type as the first implant region, but a different doping type than the channel region; a first spacer disposed adjacent to a first side of the gate region; a second spacer disposed adjacent to a second side of the gate region and having a wider width than the first spacer; and a drift region having an edge vertically aligned with an edge of the second spacer and disposed between the channel region and the second implant region. The channel region may be disposed between the first implant region and the drift region.

公开(公告)号：US10546852B2

公开(公告)日：2020-01-28

申请号：US15970618

申请日：2018-05-03

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Matthew Michael Nowak

IPC: H01L29/22 ,  H01L27/06 ,  H01L27/092 ,  H01L21/8249 ,  H01L29/93 ,  H01L29/205 ,  H01L29/737

Abstract: A semiconductor device comprises a complementary metal oxide semiconductor (CMOS) device and a heterojunction bipolar transistor (HBT) integrated on a single die. The CMOS device may comprise silicon. The HBT may comprise III-V materials. The semiconductor device may be employed in a radio frequency front end (RFFE) module to reduce size and parasitics of the RFFE module and to provide cost and cycle time savings.

公开(公告)号：US10158030B2

公开(公告)日：2018-12-18

申请号：US15431623

申请日：2017-02-13

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Gengming Tao ,  Richard Hammond ,  Ranadeep Dutta ,  Matthew Michael Nowak ,  Francesco Carobolante

IPC: H01L29/93 ,  H01L29/20 ,  H01L29/22 ,  H01L29/47 ,  H01L29/737 ,  H01L29/66 ,  H01L27/06 ,  H01L21/822 ,  H01L23/00 ,  H01L23/66 ,  H03H11/34 ,  H03H11/04

Abstract: A tunable capacitor may include a first terminal having a first semiconductor component with a first polarity. The tunable capacitor may also include a second terminal having a second semiconductor component with a second polarity. The second component may be adjacent to the first semiconductor component. The tunable capacitor may further include a first conductive material electrically coupled to a first depletion region at a first sidewall of the first semiconductor component.

公开(公告)号：US09252147B2

公开(公告)日：2016-02-02

申请号：US13958646

申请日：2013-08-05

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Choh Fei Yeap

IPC: H01L29/76 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H03F3/195 ,  H03F1/02 ,  H03F3/24 ,  H03F3/72

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/823857 ,  H01L23/66 ,  H01L27/0207 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/7833 ,  H01L2924/0002 ,  H03F1/0277 ,  H03F3/195 ,  H03F3/245 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/429 ,  H03F2200/432 ,  H03F2203/7209 ,  H03F2203/7236 ,  H01L2924/00

Abstract: A method includes forming a first gate oxide in a first region and in a second region of a wafer. The method further includes performing first processing to form a second gate oxide in the second region. The second gate oxide has a different thickness than the first gate oxide. The method also includes forming first gate material of a first device in the first region and forming second gate material of a second device in the second region. The first device corresponds to a first radio frequency (RF) band and the second device corresponds to a second RF band that is different from the first RF band.

Abstract translation: 一种方法包括在晶片的第一区域和第二区域中形成第一栅极氧化物。 该方法还包括执行第一处理以在第二区域中形成第二栅极氧化物。 第二栅极氧化物具有与第一栅极氧化物不同的厚度。 该方法还包括在第一区域中形成第一器件的第一栅极材料并在第二区域中形成第二器件的第二栅极材料。 第一设备对应于第一射频（RF）频带，第二设备对应于与第一RF频带不同的第二RF频段。

公开(公告)号：US09153691B1

公开(公告)日：2015-10-06

申请号：US14338294

申请日：2014-07-22

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L21/331 ,  H01L29/78 ,  H01L29/66 ,  G06F17/50

CPC classification number: H01L29/7835 ,  G06F17/5068 ,  G06F17/5072 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/4238 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/78624

Abstract: In one aspect, a MOS transistor includes a first diffusion region of a first doping type, a tap region of a second doping type configured to contact the first diffusion region, a channel region configured to substantially surround the first diffusion region and the tap region, and a second diffusion region of the first doping type configured to substantially surround the channel region. In another aspect, a method for manufacturing a MOS transistor includes, forming a first diffusion region of a first doping type, forming a tap region of a second doping type contacting the first diffusion region, forming a second diffusion region of the first doping type substantially surrounding the first diffusion region and the tap region, and forming a gate electrode substantially surrounding the first diffusion region and the tap region.

Abstract translation: 一方面，MOS晶体管包括第一掺杂型的第一扩散区域，被配置为接触第一扩散区域的第二掺杂类型的抽头区域，被配置为基本上围绕第一扩散区域和抽头区域的沟道区域， 以及第一掺杂类型的第二扩散区域，被配置为基本上围绕所述沟道区域。 在另一方面，一种用于制造MOS晶体管的方法包括：形成第一掺杂类型的第一扩散区，形成接触第一扩散区的第二掺杂类型的抽头区，基本上形成第一掺杂型的第二扩散区 围绕第一扩散区域和抽头区域，以及形成基本围绕第一扩散区域和抽头区域的栅电极。