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71 条记录 (耗时 0.074 秒)

    Method for fabricating silicon nanowire field effect transistor based on wet etching
    31.
    发明授权
    Method for fabricating silicon nanowire field effect transistor based on wet etching 有权
    基于湿蚀刻制造硅纳米线场效应晶体管的方法

    公开(公告)号：US09034702B2

    公开(公告)日：2015-05-19

    申请号：US13511123

    申请日：2011-11-18

    申请人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

    发明人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

    CPC分类号： H01L29/66772 ,  H01L29/42392 ,  H01L29/78696

    摘要： Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching. The method includes defining an active region; depositing a silicon oxide film as a hard mask, forming a pattern of a source and a drain and a fine bar connecting the source and the drain; transferring the pattern on the hard mask to a silicon substrate by performing etching process for the silicon substrate; performing ion implanting; etching the silicon substrate by wet etching, so that the silicon fine bar connecting the source and the drain is suspended; reducing the silicon fine bar to a nano size to form a silicon nanowire; depositing a polysilicon film; forming a polysilicon gate line acrossing the silicon nanowire by electron beam lithography and forming a structure of nanowire-all-around; forming a silicon oxide sidewall at both sides of the polysilicon gate line, by depositing a silicon oxide film and subsequently etching the silicon oxide film; forming the source and the drain by using ion implantation and high temperature annealing, so that the silicon nanowire field effect transistor is finally fabricated. The method is compatible with a conventional integrated circuit fabrication technology. The fabrication process is simple and convenient, and has a short cycle.

    摘要翻译： 本文公开了一种基于湿蚀刻制造硅纳米线场效应晶体管的方法。 该方法包括定义活动区域; 沉积氧化硅膜作为硬掩模，形成源极和漏极的图案以及连接源极和漏极的细棒; 通过对硅衬底进行蚀刻处理，将硬掩模上的图案转移到硅衬底; 进行离子注入; 通过湿蚀刻蚀刻硅衬底，使得连接源极和漏极的硅细棒悬空; 将硅细棒还原成纳米尺寸以形成硅纳米线; 沉积多晶硅膜; 通过电子束光刻形成跨越硅纳米线的多晶硅栅极线，并形成全纳米线的结构; 在多晶硅栅极线的两侧形成硅氧化物侧壁，通过沉积氧化硅膜并随后蚀刻氧化硅膜; 通过离子注入和高温退火形成源极和漏极，从而最终制造出硅纳米线场效应晶体管。 该方法与传统的集成电路制造技术相兼容。 制造工艺简单方便，循环周期短。

    Tribocharge test fixture
    32.
    发明授权
    Tribocharge test fixture 有权
    摩擦电试验夹具

    公开(公告)号：US08829912B2

    公开(公告)日：2014-09-09

    申请号：US13059869

    申请日：2009-08-26

    申请人： Xin Huang ,  Jun Hu ,  Qiang Wang

    发明人： Xin Huang ,  Jun Hu ,  Qiang Wang

    IPC分类号： G01R29/12 ,  G01N33/44 ,  G01N27/60

    CPC分类号： G01N27/60 ,  G01N33/442

    摘要： A fixture can include a test fixture that holds an object whose electrostatic charge characteristics are to be measured, means for moving a piece of rubbing material into contact with the object, and means for rubbing a surface of the object. A method for measuring the electrostatic charge characteristics of an object using a test fixture can include: placing the object in the test fixture, moving a piece of rubbing material into contact with the object and rubbing a surface of the object with the piece of rubbing material for a period of time. The rubbing causes an electrostatic charge to be built up on the surface of the object. The electrostatic charge characteristics of the object can be measured and the measured electrostatic charge characteristics of the object can be displayed.

    摘要翻译： 固定装置可以包括固定要测量其静电荷特性的物体的测试夹具，用于将一块摩擦材料移动到与物体接触的装置，以及用于摩擦物体表面的装置。 使用测试夹具测量物体的静电电荷特性的方法可以包括：将物体放置在测试夹具中，使一块摩擦材料与物体接触并用该摩擦材料摩擦物体的表面 一段时间。 摩擦会导致在物体表面上形成静电电荷。 可以测量物体的静电电荷特性，并且可以显示物体的测量的静电电荷特性。

    Low fluoride thermoplastic composition, method of manufacture and product made therefrom
    33.
    发明授权
    Low fluoride thermoplastic composition, method of manufacture and product made therefrom 有权
    低氟热塑性组合物，制造方法和由其制成的产品

    公开(公告)号：US08357739B2

    公开(公告)日：2013-01-22

    申请号：US11609094

    申请日：2006-12-11

    申请人： Xin Huang ,  Tong Sun ,  Huagui Yang ,  David Xiangping Zou

    发明人： Xin Huang ,  Tong Sun ,  Huagui Yang ,  David Xiangping Zou

    IPC分类号： C08K5/098 ,  C08K3/22 ,  C08L27/12

    CPC分类号： C08L69/00 ,  C08K3/22 ,  C08K3/26 ,  C08K5/098 ,  C08L27/18 ,  C08L2666/04

    摘要： A thermoplastic composition that includes a base polymer, a fluoropolymer, and a fluoride scavenger having suitable fluoride levels such that use in the electronics industry is appropriate. An extrusion method may be used for making the thermoplastic composition. The compositions may then be used to form a molded article. The composition has lower fluoride levels as compared to thermoplastic compositions without the fluoride scavenger making it suitable for use in electronic applications, as well as medical or food or beverage applications where fluoride ions are a concern.

    摘要翻译： 一种热塑性组合物，其包含具有合适氟化物含量的基础聚合物，含氟聚合物和氟化物清除剂，使得在电子工业中的使用是合适的。 可以使用挤出方法来制造热塑性组合物。 然后可以将组合物用于形成模塑制品。 与没有氟化物清除剂的热塑性组合物相比，组合物具有较低的氟化物水平，使其适用于电子应用，以及用于关注氟离子的医疗或食品或饮料应用。

    MOS Transistor Having Combined-Source Structure With Low Power Consumption and Method for Fabricating the Same
    34.
    发明申请
    MOS Transistor Having Combined-Source Structure With Low Power Consumption and Method for Fabricating the Same 有权
    具有低功耗的组合源结构的MOS晶体管及其制造方法

    公开(公告)号：US20120313154A1

    公开(公告)日：2012-12-13

    申请号：US13501241

    申请日：2011-10-14

    申请人： Ru Huang ,  Qianqian Huang ,  Zhan Zhan ,  Xin Huang ,  Yangyuan Wang

    发明人： Ru Huang ,  Qianqian Huang ,  Zhan Zhan ,  Xin Huang ,  Yangyuan Wang

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/7839

    摘要： The present invention discloses a MOS transistor having a combined-source structure with low power consumption, which relates to a field of field effect transistor logic devices and circuits in CMOS ultra-large-scaled integrated circuits. The MOS transistor includes a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a Schottky source region, a highly-doped source region and a highly-doped drain region. An end of the control gate extends to the highly-doped source region to form a T shape, wherein the extending region of the control gate is an extending gate and the remaining region of the control gate is a main gate. The active region covered by the extending gate is a channel region, and material thereof is the substrate material. A Schottky junction is formed between the Schottky source region and the channel under the extending gate. The combined-source structure according to the invention combines a Schottky barrier and a T-shaped gate, improves the performance of the device, and the fabrication method thereof is simple. Thus, a higher turn-on current, a lower leakage current, and a steeper subthreshold slope can be obtained, and the present application can be applied in the field of low power consumption and have a higher practical value.

    摘要翻译： 本发明公开了一种具有低功耗的组合源结构的MOS晶体管，其涉及CMOS超大规模集成电路中的场效应晶体管逻辑器件和电路领域。 MOS晶体管包括控制栅极电极层，栅极电介质层，半导体衬底，肖特基源区，高掺杂源极区和高掺杂漏极区。 控制栅极的一端延伸到高掺杂源极区域以形成T形，其中控制栅极的延伸区域是延伸栅极，控制栅极的其余区域是主栅极。 由延伸栅极覆盖的有源区是沟道区，其材料是衬底材料。 在肖特基源区域和延伸栅极下方的通道之间形成肖特基结。 根据本发明的组合源结构组合了肖特基势垒和T形门，提高了器件的性能，其制造方法简单。 因此，可以获得更高的导通电流，较低的漏电流和更陡的亚阈值斜率，并且本申请可以应用于低功耗领域并具有较高的实用价值。

    METHOD FOR ACHIEVING FOUR-BIT STORAGE USING FLASH MEMORY HAVING SPLITTING TRENCH GATE
    38.
    发明申请
    METHOD FOR ACHIEVING FOUR-BIT STORAGE USING FLASH MEMORY HAVING SPLITTING TRENCH GATE 有权
    使用具有分割式闸门的闪存存储器实现四位存储的方法

    公开(公告)号：US20120188821A1

    公开(公告)日：2012-07-26

    申请号：US13499596

    申请日：2011-10-14

    申请人： Yimao Cai ,  Ru Huang ,  Shiqiang Qin ,  Poren Tang ,  Yu Tang ,  Shenghu Tan ,  Xin Huang ,  Yue Pan

    发明人： Yimao Cai ,  Ru Huang ,  Shiqiang Qin ,  Poren Tang ,  Yu Tang ,  Shenghu Tan ,  Xin Huang ,  Yue Pan

    IPC分类号： G11C16/34

    CPC分类号： H01L29/42352 ,  G11C16/0475 ,  H01L29/7887 ,  H01L29/7923

    摘要： The present invention discloses a method for achieving four-bit storage by using a flash memory having a splitting trench gate. The flash memory with the splitting trench gate is disclosed in a Chinese patent No. 200710105964.2. At one side that each of two trenches is contacted with a channel, a programming for electrons is achieved by using a channel hot electron injection method; and at the other side that each of the two trenches is contacted with a source or a drain, a programming for electrons is achieved by using an FN injection method, so that a function of a four-bit storage of the device is achieved by changing a programming mode. Thus, a performance of the device is improved while a storage density is greatly increased.

    摘要翻译： 本发明公开了一种通过使用具有分割沟槽栅的闪存来实现四位存储的方法。 具有分割沟槽栅的闪速存储器在中国专利No.200710105964.2中公开。 在两个沟槽中的每一个与沟道接触的一侧，通过使用沟道热电子注入方法实现电子编程; 并且在另一侧，两个沟槽中的每一个与源极或漏极接触，通过使用FN注入方法来实现电子编程，使得通过改变器件的四位存储器的功能来实现 一种编程模式。 因此，提高了存储密度的装置的性能。

    TRIBOCHARGE TEST FIXTURE
    39.
    发明申请
    TRIBOCHARGE TEST FIXTURE 有权
    TRIBOCHARGE测试仪器

    公开(公告)号：US20110148427A1

    公开(公告)日：2011-06-23

    申请号：US13059869

    申请日：2009-08-26

    申请人： Xin Huang ,  Jun Hu ,  Qiang Wang

    发明人： Xin Huang ,  Jun Hu ,  Qiang Wang

    IPC分类号： G01R29/12

    CPC分类号： G01N27/60 ,  G01N33/442

    摘要： A fixture can include a test fixture that holds an object whose electrostatic charge characteristics are to be measured, means for moving a piece of rubbing material into contact with the object, and means for rubbing a surface of the object. A method for measuring the electrostatic charge characteristics of an object using a test fixture can include: placing the object in the test fixture, moving a piece of rubbing material into contact with the object and rubbing a surface of the object with the piece of rubbing material for a period of time. The rubbing causes an electrostatic charge to be built up on the surface of the object. The electrostatic charge characteristics of the object can be measured and the measured electrostatic charge characteristics of the object can be displayed.

    摘要翻译： 固定装置可以包括固定要测量其静电荷特性的物体的测试夹具，用于将一块摩擦材料移动到与物体接触的装置，以及用于摩擦物体表面的装置。 使用测试夹具测量物体的静电电荷特性的方法可以包括：将物体放置在测试夹具中，使一块摩擦材料与物体接触并用该摩擦材料摩擦物体的表面 一段时间。 摩擦会导致在物体表面上形成静电电荷。 可以测量物体的静电电荷特性，并且可以显示物体的测量的静电电荷特性。